FPGA-像素操作（二值图片，异或操作，暗通道rgb）

像素操作（二值图片，异或操作，暗通道rgb）`timescale1ns/1ps//------------------------------------------------/*mode=1XOR;(异或图像)
mode=2Black&white(二值图像)
mode=3lessbright (暗通道);
*/moduleRGB_proc(
clk,
rst_n,
mode,
RGB_in,
RGB_out,
i_h_sync, 
i_v_sync, 
i_data_en,
o_h_sync, 
o_v_sync, 
o_data_en);
inputi_h_sync ;
inputi_v_sync ;
inputi_data_en;
inputclk,rst_n;
input  [1:0]  mode;  
input  [23:0] RGB_in; //inputRGBoutput [23:0] RGB_out; //outpuRGBoutputrego_h_sync;
outputrego_v_sync;
outputrego_data_en;
wire [7:0] R, G, B;
wire [7:0] R1, G1, B1;
wire [7:0] R2, G2, B2;
wire [7:0] R3, G3, B3;
reg  [7:0] R_out, G_out, B_out;
assignRGB_out= {B_out, G_out, R_out};
assignR=RGB_in[7:0];
assignG=RGB_in[15:8];
assignB=RGB_in[23:16]; 
assignR1=R^8'b1111_1111;assignG1=R^8'b1111_1111;assignB1=R^8'b1111_1111;assignR3= (R<'h40) ? 'd0 : R-'h40;assignG3= (G<'h40) ? 'd0 : G-'h40;assignB3= (B<'h40) ? 'd0 : B-'h40;assignR2=R;
assignG2=R;
assignB2=R;
always@(posedgeclk, negedgerst_n)beginif (rst_n==1'b0) beginR_out<=0;
G_out<=0;
B_out<=0;
endelseif (mode==1) beginR_out<=R1;
G_out<=G1;
B_out<=B1;
endelseif (mode==2) beginR_out<=R2;
G_out<=G2;
B_out<=B2;
endelseif (mode==3) beginR_out<=R3;
G_out<=G3;
B_out<=B3;
endelsebeginR_out<=R;
G_out<=G;
B_out<=B;
endendalways@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)begino_h_sync<=1'b0;o_v_sync<=1'b0;o_data_en<=1'b0;endelsebegino_h_sync<=i_h_sync;
o_v_sync<=i_v_sync;
o_data_en<=i_data_en;
endendendmodule