RISC-V开发工具 | 使用CDS进行RISC-V硬件平台的开发和调试-阿里云开发者社区

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RISC-V开发工具 | 使用CDS进行RISC-V硬件平台的开发和调试

简介: 背景 本视频是给open hardware组织展示使用,open hardware开源了一个RISCV的硬件代码:CORE-V,并且提供了FPGA作为演示平台。本视频第一部分:使用对应的FPGA,演示如何通过CDS,创建、编译并且在FPGA上调试CORE-V CPU的程序。 第二部分,为了显示CDS与其他同样支持CORE-V平台的IDE的不同指出,CDS推出了Profiling功能,并且配置了CORE-V虚拟平台,并且演示了与第一个工程同样的工程。

全文中英文
Hello everyone, my name is Peter, and I come from Alibaba Group. Today I am very happy to introduce a new development tool for CORE-V platform. CDS, the full name is Chip Development Suite.
大家好,我是来自阿里巴巴的Peter。今天我非常高兴给大家介绍一款CORE-V平台的开发工具,CDS,全程是Chip Development Suite

CDS is an eclipse-based graphical development tool, and we use eclipse plus more than 40 plug-ins to makes it into CDS. With CDS, a developer can create a new project based on CORE-V core, then coding and building the project. CDS also provides the flash loader and debugger which can help developers download images into target and debug the target in a graphical debugger view.
CDS是一款基于eclipse的图形开发工具,我们在eclipse基础上增加了超过40个插件,从而变成了CDS,使用CDS,开发者可以创建基于CORE-V核的工程,并且能够进行代码开发和编译。CDS也提供了Flash下载器、调试器等,这些工具可以帮助开发者将程序镜像下载到嵌入式设备端,并进行图形化的调试。

So, today I will give you a show about how to create and debug a CORE-V project in CDS. Before the presentation, we should do some preparation:
今天我将给大家演示,如何在CDS中创建和调试一个CORE-V的工程。在演示之前,我们需要做一些准备工作。

We will use GENESYS2 FPGA board to simulate a CORE-V platform, I have prepared the bit files which uses the default USB cable for debugging, and I got the SDK from github: the pulp-runtime project and the pulp-runtime-examples project. In CDS, we use some examples from the pulp-runtime-examples project, and put the source files together with pulp-runtime project, and make these files into CDS projects. Besides, I have configured the board with “USB/SD” config mode to start GENESYS2 board.
我们使用GENESYS2 FPGA开发板来模拟CORE-V硬件平台,工程使用github上开源的pulp-runtime工程。在CDS中,我们使用了一些从github上下载的开源例程。我已经配置了GENESYS2开发板为USB/SD的工作模式。

Before starting CDS, we should connect the GENESYS2 board at first. Just prepare one USB line, and connect it from computer’s USB port to the USB cable for debugging on GNENSYS2 board.
启动CDS之前,我们需要准备一个USB线,一端连接电脑,一段连接GENESYS2开发板上的USB调试口。

After this preparation, we can start CDS in PC, just double click the icon in the desktop, and then choose a folder as the workspace in CDS.
上手准备完成以后,我们可以启动CDS,只需要双击双面CDS图标,然后选择一个目录作为CDS工作空间。

when enter the workspace at the first time, CDS will show the welcome page, we can create the project by clicking “project creator”, and also, we can create a project in project explorer view. Right click blank area in project explorer, chose T-Head CPU project, and in the popup dialog, we can see all the project templates which supported by CDS. Here we have added CORE-V project templates into CDS, a user can find CORE-V platform in “Target Template Selected” tree view. Now there are two project templates here, we chose the simple as the template to create a new CORE-V project, just input project name, and click finish.
首次进入工作空间,CDS将会显示welcome页面,我们可以点击project creator图标进行工程创建,也可以在工程窗口中创建工程。右击工程窗口空白位置,选择T-HEAD CPU工程,然后弹出对话框,我们可以看到CDS支持的全部工程模板。这里我们已经将CORE-V工程模板加入CDS中,用户可以在Target Template Select视图中找到CORE-V平台。现在这里有两个CORE-V工程,我们选择一个简单的工程模板用来创建一个全新的CORE-V工程,在这里输入工程名,点击Finish

After finish creating project, we can right click project node, and start to build our project.
完成工程创建,我们右击工程节点,选择build工程

Now project is built successfully, next, we can start to debug it on the GENESYS2 board. Just right click the project and chose “Debug As-> T-Head Application”. Then CDS goes into the debug perspective, connects the board and automatically downloads the images into the GENESYS2 board and then auto run the program into main, just like this.
现在工程成功编译,我们可以在GENESYS2开发板上进行调试。直接右击工程,选择Debug As->T-Head Application,然后CDS进入了调试视图,连接开发板,并自动将程序下载到GENESYS2开发板中,最后运行程序到main函数,就像当前这样。

When success to go to main function, CDS has been in debug perspective, in this perspective, we can control the board’s state, we can run the board by click continue button, we can also let the board execute the project by stepping the source code, just like this.
但我们进入main函数以后,CDS已经在调试视图中了,在这里视图夏,我们可以控制开发板的状态,我们可以通过点击continue按钮运行开发板,我们可以点击单步按钮,单步执行我们的工程,就像这样。

In “Disassembly View”, we can see the current position of the program, and see the next instructions which will be executed by CORE-V CPU.
在反汇编窗口中,我们可以看到当前程序的位置,并且可以看到后续CORE-V CPU即将执行的指令。

And in “Debug View”, we can see the call stacks of the program, and find the source code by click each frame, besides, the disassembly view also changes the display according to the selected frame
在Debug视图中,我们可以看到程序的调用栈,并且通过点击每个帧,可以看到对应帧的源代码,此时反汇编窗口也会显示对应的指令。

We can read and write the CORE-V’s registers in the “Register View”, To access the variables of the program, we should use “Variable view”. In the “Expression View”, we can input any variable or symbol of our project, and read it or modify it.
我们可以在寄存器窗口中读写CORE-V的寄存器。变量窗口中可以访问程序的变量。在表达式窗口中,我们可以输入工程中的任何符号,并且可以读写符号对应的内存值。

So, that is the first part of my presentation about how to develop and debug a CORE-V platform with CDS.
以上是我们的第一部分演示,演示了如何在CDS中开发和调试一个CORE-V平台

For the above demo, I must say thanks to Hugh, because he helps me a lot about how to start the GENESYS2 board, and with his help, I can integrate CORE-V project into CDS in a short time.
关于上述demo,我非常感谢Hugh(CORE-V的一个人员),因为他给了我很多的帮助,让我们能够启动GENSYS2开发板,并且在他的帮助夏,我很快地将CORE-V工程集成到了CDS中。

Now, I want to show another powerful feature of our CDS, it’s called “T-Head Profiling”
现在,我将给你们展示CDS的另外一个重要功能,T-Head Profiling

As we have known, CDS is an IoT IDE for CORE-V cores, in CDS, a user can create, build and debug a CORE-V based project, besides, CDS provides many other functions which will help developer create a high performance and low power images as soon as possible, the “T-Head Profiling” is one of those functions.
正如我们所知道的,CDS是一个开发调试CORE-V的IoT集成开发环境,用户可以在CDS中创建、调试CORE-V工程,此外,CDS还提供了其他可以帮助开发者开发出高性能、低功耗镜像的功能,T-Head Profiling就是其中一个。

In CDS, we can start the T-Head profiling for some project in an easy way, now I will show it.
在CDS中,我们可以很方便地为一些工程启动T-Head Profiling功能,现在我将演示一下。

Here is the same project that I just created, we can see the main logic, this is some simple arithmetic operations.
这里是我刚刚创建的工程,我们可以看到main函数的逻辑,这里有一些简单的算术操作。

If these operations are part of a real logic for some algorithm, there will be a very practical question: what is the hotspot code block of this algorithm? and which function should I put more energy to optimize? The answer is using CDS “T-Head Profiling”
加入这里的操作逻辑是一个真实的算法中的一部分,那么将会有个工程性的问题:这个算法的热点代码是什么?我应该在哪个函数上花较多的精力去优化?使用CDS的T-Head Profiling功能将很好地解决这些问题。

Right now, the “t-head profiling” only support project which will run in the simulator instead of real hardware, so here we have configured a simulated platform for this CORE-V project, let me show it, just right click project and select profile configuration, double click t-head profiling, then we success to create a profiling configuration for our project, we can see the project has the default platform, xxxxxxx
目前,T-Head Profiling功能仅支持模拟器运行,所以这里我们配置了一个CORE-V工程的模拟平台。右击工程,选择Profile Configuration,双击T-Head Profiling,然后我们成功的创建了一个profiling配置,我们可以看到种类默认的虚拟平台。

We can click profile to start t-head profiling, CDS will show the “Profiling Running” page… in this page, we could see the dynamic situation of the program’s execution which includes hotspot function rank, the memory access, interrupt and fast interrupt info.
我们可以点击Profile来启动T-Head Profiling功能,CDS将会显示Profiling Running页面,在这个页面中给,我们可以看到程序的动态运行状态,包括热点函数排序、内存访问、中断信息。

After click “Finish Profiling” button, “Profiling Overview” page pops up, this page shows the cycles rank of five top functions, Here shows the instructions total number of each instruction type. It also shows the I/D cache miss rate & branch predict rate, for those CPUs which have such hardware modules.
点击Finish Profiling按钮以后,会弹出Profiling Overview页面,在这个页面中,会展示周期前五的函数,这里会展每个指令类型的总数,还有为哪些包含相关硬件的CPU展示cache miss率和分支预测准确率。

The “TimeLine” page gives the whole execution lifetime of the program, we can see the instruction stream of any range of the lifetime. When we double click any time point in timeline, the executed instructions during this time range will show here, by double clicking each line of the list, we will locate the corresponding source code. We can also narrow the time line, and see the detail executed instructions info.
TimeLine页面展示了程序运行的全部运行时间,我们可以看到整个程序运行的指令流,我们可以双击任何时间点,此时刻的指令流会显示在这里,双击每个指令,可以看到该指令对应的源代码。我们可以通过缩短时间线,来看到程序执行流的细节信息。

In the “Function” page, we can see all functions list, the instruction column shows the total instructions in this function except its sub functions, the cycle column shows total cycles in the function except its sub functions. we can click each column header to rank the list according to the column header.
在Function页面中,我们可以看到全部函数列表,insn列显示了当前函数执行的指令总数,cycle列显示了当前函数执行的周期数。通过点击每个列,可以按照该列对当前函数进行排序。

The last but not the least, the “Call Paths” view. This view shows the dynamic call paths of the program, this page’s columns are similar with “Function” page, but the page shows a tree view instead of a list. In Call Paths tree, we can see the dynamical execution call path, and we can find each function’s instructions and cycles info in that path.
最后,Call Paths视图显示了程序动态调用轨迹。该页面的列类似于Function视图,但是种类使用了树形展示,在Call Paths树中,我们可以看到程序动态调用路径,我们可以找到每个函数的指令和周期信息。

And that’s all for the T-Head Profiling, I hope this function can help users optimize the program which run in CORE-V platform
以上就是T-Head Profiling的全部功能,希望这个功能可以帮助开发人员优化运行在CORE-V平台上的程序。

Thanks for your attention.
感谢。

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