# 【黑金原创教程】【FPGA那些事儿-驱动篇I 】【实验一】流水灯模块

#### 实验一：流水灯模块

##### led_funcmod.v
1.    module led_funcmod
2.    (
3.         input CLOCK, RESET,
4.         output [3:0]LED
5.    );

6.         parameter T1S = 26'd50_000_000; //1Hz
7.         parameter T100MS = 26'd5_000_000; //10Hz
8.         parameter T10MS = 26'd500_000; //100Hz
9.         parameter T1MS = 26'd50_000; //1000Hz
10.

11.         reg [3:0]i;
12.         reg [25:0]C1;
13.         reg [3:0]D;
14.         reg [25:0]T;
15.         reg [3:0]isTag;
16.
17.         always @ ( posedge CLOCK or negedge RESET )
18.             if( !RESET )
19.                  begin
20.                         i <= 4'd0;
21.                         C1 <= 26'd0;
22.                         D <= 4'b0001;
23.                         T <= T1S;
24.                         isTag <= 4'b0001;
25.                    end
26.              else

27.                case( i )
28.
29.                      0:
30.                      if( C1 == T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
31.                      else begin C1 <= C1 + 1'b1; D <= 4'b0001; end
32.
33.                      1:
34.                      if( C1 == T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
35.                      else begin C1 <= C1 + 1'b1; D <= 4'b0010; end
36.
37.                      2:
38.                      if( C1 == T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
39.                      else begin C1 <= C1 + 1'b1; D <= 4'b0100; end
40.
41.                      3:
42.                      if( C1 == T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
43.                      else begin C1 <= C1 + 1'b1; D <= 4'b1000; end
44.
45.                      4:
46.                      begin isTag <= { isTag[2:0], isTag[3] }; i <= i + 1'b1; end
47.
48.                      5:
49.                      if( isTag[0] ) begin T <= T1S; i <= 4'd0; end
50.                      else if( isTag[1] ) begin T <= T100MS; i <= 4'd0; end
51.                      else if( isTag[2] ) begin T <= T10MS; i <= 4'd0; end
52.                      else if( isTag[3] ) begin T <= T1MS; i <= 4'd0; end
53.
54.              endcase
55.

56.        assign LED = D;
57.
58.    endmodule

1.           0:
2.          if( C1 == T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
3.          else begin C1 <= C1 + 1'b1; D <= 4'b0001; end
4.          1:
5.          if( C1 == T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
6.          else begin C1 <= C1 + 1'b1; D<= 4'b0010; end
7.          2:
8.          if( C1 ==T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
9.          else begin C1 <= C1 + 1'b1; D <= 4'b0100; end
10.          3:
11.          if( C1 == T -1) begin C1 <= 26'd0; i <= i + 1'b1; end
12.          else begin C1 <= C1 + 1'b1; D <= 4'b1000; end

1.        reg [3:0] D = 4’b0001;
2.        ......
3.        0,1,2,3：
4.        if( C1 == T -1) begin D <= { D[2:0], D[3] }; C1 <= 26'd0; i <= i + 1'b1; end
5.        else begin C1 <= C1 + 1'b1; end

+ 订阅