数字逻辑电路实验：基本电子钟

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
entity count_24 is
port(clk,en,rst:in std_logic;
  c1,c0:out std_logic_vector(3 downto 0);
  co:out std_logic);
end count_24;
architecture one of count_24 is
  begin
  process(clk)
    variable mc1,mc0:std_logic_vector(3 downto 0):="0000";
    begin
      if rst='1' then 
        mc1:=(others=>'0');
        mc0:=(others=>'0');
      elsif clk'event and clk='1'then
        if en='1' then
          mc0:=mc0+1;
          if mc0="1010"then
            mc1:=mc1+1;
            mc0:="0000";
          end if;
          if (mc1="0010")and(mc0="0100")then
            mc0:="0000";
            mc1:="0000";
            co<='1';
          else co<='0';
        end if;
      end if;
    end if;
  c1<=mc1;
  c0<=mc0;
end process;
end one;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_60 is
port(
      clk,rst,en:in std_logic;
      c1,c0:buffer  std_logic_vector(3 downto 0);--个位与十位
    co:out std_logic--进位输出
    );
end count_60;
architecture one of count_60 is
begin
  process(clk,rst)
  variable mc1,mc0:std_logic_vector(3 downto 0);
  begin
    if rst='1' then 
      mc1:=(others=>'0');
      mc0:=(others=>'0');
    elsif clk'event and clk='1' then
      if en='1' then
       if mc0<9 then mc0:=mc0+1; co<='0';
        elsif mc1<5 then 
          mc1:=mc1+1;
          mc0:=(others=>'0');
        elsif mc1=5 and mc0=9 then
          co<='1';
          mc1:=(others=>'0');
          mc0:=(others=>'0');
        else co<='0';
        end if;
      end if;
    end if;
    c1<=mc1;
    c0<=mc0;
  end process;
end one;    

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dev is
port(clk_1khz:in std_logic;
clk_1hz:out std_logic);
end;
architecture beha of dev is
  signal q1:integer range 0 to 999;
  begin
    process(clk_1khz) begin
      if clk_1khz'event and clk_1khz='1' then
        if q1<500 then q1<=q1+1;clk_1hz<='0';
        elsif q1<999 then q1<=q1+1;clk_1hz<='1';
        else q1<=0;
      end if;
      end if;
    end process;
  end;  

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seltime is
  port(clk:in std_logic;
    h,m,s:in std_logic_vector(7 downto 0);
    sel:out std_logic_vector(2 downto 0);
    seg:out std_logic_vector(6 downto 0));
end seltime;
architecture beha of seltime is
  signal scan_count:std_logic_vector(2 downto 0);
  signal dat:std_logic_vector(3 downto 0);
  begin
    scan:process(clk)
      begin
        if clk'event and clk='1' then
scan_count<=scan_count+1;
        end if;
      sel<=scan_count;
      case scan_count is
        when "111"=>dat<=s(3 downto 0);
        when "110"=>dat<=s(7 downto 4);
        when "101"=>dat<=m(3 downto 0);
        when "100"=>dat<=m(7 downto 4);
        when "011"=>dat<=h(3 downto 0);
        when "010"=>dat<=h(7 downto 4);
        when others=>NULL;
      end case;
    end process scan;
  decode:process(scan_count) begin
    case dat is
      when"0000"=>seg<="0111111";
      when"0001"=>seg<="0000110";
      when"0010"=>seg<="1011011";
      when"0011"=>seg<="1001111";
      when"0100"=>seg<="1100110";
      when"0101"=>seg<="1101101";
      when"0110"=>seg<="1111101";
      when"0111"=>seg<="0000111";
      when"1000"=>seg<="1111111";
      when"1001"=>seg<="1101111";
      when others=>seg<="1000000";
      end case;
    end process decode;
  end beha;