Linux移植:正点原子阿尔法IMX6ULL开发板Linux内核源码移植详细步骤(4.1.15版本内核)(下)

简介: Linux移植:正点原子阿尔法IMX6ULL开发板Linux内核源码移植详细步骤(4.1.15版本内核)(下)

4 保存修改后的图形化配置文件

在修改网络驱动的时候我们通过图形界面使能了 LAN8720A 的驱动,使能以后会在.config中存在如下代码:

CONFIG_SMSC_PHY=y

打开 drivers/net/phy/Makefile,有如下代码:

obj-$(CONFIG_SMSC_PHY) += smsc.o

当 CONFIG_SMSC_PHY=y 的时候就会编译 smsc.c 这个文件, smsc.c 就是 LAN8720A 的驱动文件。但是当我们执行“make clean”清理工程以后.config 文件就会被删除掉,因此我们所有的配置内容都会丢失,结果就是前功尽弃,一“删”回到解放前!所以我们在配置完图形界面以后经过测试没有问题,就必须要保存一下配置文件。保存配置的方法有两个。

1、直接另存为.config 文件

既然图形化界面配置后的配置项保存在.config 中,那么就简单粗暴,直接将.config 文件另存为 imx_alientek_emmc_defconfig , 然后其复制到 arch/arm/configs 目录下, 替换以前的imx_alientek_emmc_defconfig。这样以后执行“make imx_alientek_emmc_defconfig”重新配置Linux 内核的时候就会使用新的配置文件,默认就会使能LAN8720A 的驱动。

2、通过图形界面保存配置文件

相比于第 1 种直接另存为.config 文件,第 2 种方法就很“文雅”了,在图形界面中保存配

置文件,在图形界面中会有“< Save >”选项,如图所示

通过键盘的“→”键,移动到“< Save >”选项,然后按下回车键,打开文件名输入对话框

在图中输入要保存的文件名,可以带路径,一般是相对路径(相对于 Linux 内核源码 根目 录 )。 比如 我们要 将新 的配 置文 件保存 到目 录 arch/arm/configs 下 , 文件 名为imx_alientek_emmc_defconfig,也就是用新的配置文件替换掉老的默认配置文件。那么我们在图中输入“arch/arm/configs/imx_alientek_emmc_defconfig”即可,如图所示:

设置好文件名以后选择下方的“ < Ok >”按钮,保存文件并退出。退出以后再打开imx_alientek_emmc_defconfig 文件,就会在此文件中找到“CONFIG_SMSC_PHY=y”这一行,如图所示:

同样的,使用“make imx_alientek_emmc_defconfig”重新配置 Linux 内核的时候,LAN8720A的驱动就会使能,并被编译进Linux 镜像文件 zImage 中。

然后重新编译一下 Linux 内核

关于Linux 内核的移植就讲解到这里,简单总结一下移植步骤:

①、在 Linux 内核中查找可以参考的板子,一般都是半导体厂商自己做的开发板。

②、编译出参考板子对应的 zImage 和.dtb 文件。

③、使用参考板子的 zImage 文件和.dtb 文件在我们所使用的板子上启动 Linux 内核,看能

否启动。

④、如果能启动的话就万事大吉,如果不能启动那就悲剧了,需要调试 Linux 内核。不过一般都会参考半导体官方的开发板设计自己的硬件,所以大部分情况下都会启动起来。启动Linux 内核用到的外设不多,一般就 DRAM(Uboot 都初始化好的)和串口。作为终端使用的串口一般都会参考半导体厂商的 Demo 板。

⑤、修改相应的驱动,像NAND Flash、EMMC、SD 卡等驱动官方的 Linux 内核都是已经提供好了,基本不会出问题。重点是网络驱动,因为 Linux 驱动开发一般都要通过网络调试代码,所以一定要确保网络驱动工作正常。如果是处理器内部 MAC+外部 PHY 这种网络方案的话,一般网络驱动都很好处理,因为在 Linux 内核中是有外部 PHY 通用驱动的。只要设置好复位引脚、PHY 地址信息基本上都可以驱动起来。

⑥、Linux 内核启动以后需要根文件系统,如果没有根文件系统的话肯定会崩溃,所以确定 Linux内核移植成功以后就要开始根文件系统的构建。

其他修改(重点,参考原子教程移植后依旧有错误,需要按下列内容修改设备树):

上述时正点原子教程提供的移植,但在移植过后,出现了好些问题,参考教程移植后,根本无法进入系统,在不断探索后终于知道设备树内容还要大改,下面时移植玩上面内容后的设备树

代码对比软件

原来

/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"
/ {
    model = "Freescale i.MX6 ULL 14x14 EVK Board";
    compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
    chosen {
        stdout-path = &uart1;
    };
    memory {
        reg = <0x80000000 0x20000000>;
    };
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        linux,cma {
            compatible = "shared-dma-pool";
            reusable;
            size = <0x14000000>;
            linux,cma-default;
        };
    };
    backlight {
        compatible = "pwm-backlight";
        pwms = <&pwm1 0 5000000>;
        brightness-levels = <0 4 8 16 32 64 128 255>;
        default-brightness-level = <6>;
        status = "okay";
    };
    pxp_v4l2 {
        compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
        status = "okay";
    };
    regulators {
        compatible = "simple-bus";
        #address-cells = <1>;
        #size-cells = <0>;
        reg_can_3v3: regulator@0 {
            compatible = "regulator-fixed";
            reg = <0>;
            regulator-name = "can-3v3";
            regulator-min-microvolt = <3300000>;
            regulator-max-microvolt = <3300000>;
            gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
        };
        reg_sd1_vmmc: regulator@1 {
            compatible = "regulator-fixed";
            regulator-name = "VSD_3V3";
            regulator-min-microvolt = <3300000>;
            regulator-max-microvolt = <3300000>;
            gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
            enable-active-high;
        };
        reg_gpio_dvfs: regulator-gpio {
            compatible = "regulator-gpio";
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_dvfs>;
            regulator-min-microvolt = <1300000>;
            regulator-max-microvolt = <1400000>;
            regulator-name = "gpio_dvfs";
            regulator-type = "voltage";
            gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
            states = <1300000 0x1 1400000 0x0>;
        };
    };
    sound {
        compatible = "fsl,imx6ul-evk-wm8960",
               "fsl,imx-audio-wm8960";
        model = "wm8960-audio";
        cpu-dai = <&sai2>;
        audio-codec = <&codec>;
        asrc-controller = <&asrc>;
        codec-master;
        gpr = <&gpr 4 0x100000 0x100000>;
        /*
                 * hp-det = <hp-det-pin hp-det-polarity>;
         * hp-det-pin: JD1 JD2  or JD3
         * hp-det-polarity = 0: hp detect high for headphone
         * hp-det-polarity = 1: hp detect high for speaker
         */
        hp-det = <3 0>;
        hp-det-gpios = <&gpio5 4 0>;
        mic-det-gpios = <&gpio5 4 0>;
        audio-routing =
            "Headphone Jack", "HP_L",
            "Headphone Jack", "HP_R",
            "Ext Spk", "SPK_LP",
            "Ext Spk", "SPK_LN",
            "Ext Spk", "SPK_RP",
            "Ext Spk", "SPK_RN",
            "LINPUT2", "Mic Jack",
            "LINPUT3", "Mic Jack",
            "RINPUT1", "Main MIC",
            "RINPUT2", "Main MIC",
            "Mic Jack", "MICB",
            "Main MIC", "MICB",
            "CPU-Playback", "ASRC-Playback",
            "Playback", "CPU-Playback",
            "ASRC-Capture", "CPU-Capture",
            "CPU-Capture", "Capture";
    };
    spi4 {
        compatible = "spi-gpio";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spi4>;
        /* pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; */
        status = "okay";
        gpio-sck = <&gpio5 11 0>;
        gpio-mosi = <&gpio5 10 0>;
        /* cs-gpios = <&gpio5 7 0>;*/    
         num-chipselects = <1>;
        #address-cells = <1>;
        #size-cells = <0>;
        gpio_spi: gpio_spi@0 {
            compatible = "fairchild,74hc595";
            gpio-controller;
            #gpio-cells = <2>;
            reg = <0>;
            registers-number = <1>;
            registers-default = /bits/ 8 <0x57>;
            spi-max-frequency = <100000>;
        };
    };
};
&cpu0 {
    arm-supply = <&reg_arm>;
    soc-supply = <&reg_soc>;
    dc-supply = <&reg_gpio_dvfs>;
};
&clks {
    assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <786432000>;
};
&csi {
    status = "okay";
    port {
        csi1_ep: endpoint {
            remote-endpoint = <&ov5640_ep>;
        };
    };
};
&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet1
                 &pinctrl_enet1_reset>;
    phy-mode = "rmii";
    phy-handle = <&ethphy0>;
    phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
    phy-reset-duration = <200>;
    status = "okay";
};
&fec2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet2
                 &pinctrl_enet1_reset>;
    phy-mode = "rmii";
    phy-handle = <&ethphy1>;
    phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
    phy-reset-duration = <200>;
    status = "okay";
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        ethphy0: ethernet-phy@0 {
            compatible = "ethernet-phy-ieee802.3-c22";
            smsc,disable-energy-detect;
            reg = <0>;
        };
        ethphy1: ethernet-phy@1 {
            compatible = "ethernet-phy-ieee802.3-c22";
            smsc,disable-energy-detect;
            reg = <1>;
        };
    };
};
&flexcan1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_flexcan1>;
    xceiver-supply = <&reg_can_3v3>;
    status = "okay";
};
&flexcan2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_flexcan2>;
    xceiver-supply = <&reg_can_3v3>;
    status = "okay";
};
&gpc {
    fsl,cpu_pupscr_sw2iso = <0x1>;
    fsl,cpu_pupscr_sw = <0x0>;
    fsl,cpu_pdnscr_iso2sw = <0x1>;
    fsl,cpu_pdnscr_iso = <0x1>;
    fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};
&i2c1 {
    clock-frequency = <100000>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_i2c1>;
    status = "okay";
    mag3110@0e {
        compatible = "fsl,mag3110";
        reg = <0x0e>;
        position = <2>;
    };
    fxls8471@1e {
        compatible = "fsl,fxls8471";
        reg = <0x1e>;
        position = <0>;
        interrupt-parent = <&gpio5>;
        interrupts = <0 8>;
    };
};
&i2c2 {
    clock_frequency = <100000>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_i2c2>;
    status = "okay";
    codec: wm8960@1a {
        compatible = "wlf,wm8960";
        reg = <0x1a>;
        clocks = <&clks IMX6UL_CLK_SAI2>;
        clock-names = "mclk";
        wlf,shared-lrclk;
    };
    ov5640: ov5640@3c {
        compatible = "ovti,ov5640";
        reg = <0x3c>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_csi1>;
        clocks = <&clks IMX6UL_CLK_CSI>;
        clock-names = "csi_mclk";
        pwn-gpios = <&gpio_spi 6 1>;
        rst-gpios = <&gpio_spi 5 0>;
        csi_id = <0>;
        mclk = <24000000>;
        mclk_source = <0>;
        status = "okay";
        port {
            ov5640_ep: endpoint {
                remote-endpoint = <&csi1_ep>;
            };
        };
    };
};
&iomuxc {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_hog_1>;
    imx6ul-evk {
        pinctrl_hog_1: hoggrp-1 {
            fsl,pins = <
                MX6UL_PAD_UART1_RTS_B__GPIO1_IO19    0x17059 /* SD1 CD */
                MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
                MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
            >;
        };
        pinctrl_csi1: csi1grp {
            fsl,pins = <
                MX6UL_PAD_CSI_MCLK__CSI_MCLK        0x1b088
                MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK    0x1b088
                MX6UL_PAD_CSI_VSYNC__CSI_VSYNC        0x1b088
                MX6UL_PAD_CSI_HSYNC__CSI_HSYNC        0x1b088
                MX6UL_PAD_CSI_DATA00__CSI_DATA02    0x1b088
                MX6UL_PAD_CSI_DATA01__CSI_DATA03    0x1b088
                MX6UL_PAD_CSI_DATA02__CSI_DATA04    0x1b088
                MX6UL_PAD_CSI_DATA03__CSI_DATA05    0x1b088
                MX6UL_PAD_CSI_DATA04__CSI_DATA06    0x1b088
                MX6UL_PAD_CSI_DATA05__CSI_DATA07    0x1b088
                MX6UL_PAD_CSI_DATA06__CSI_DATA08    0x1b088
                MX6UL_PAD_CSI_DATA07__CSI_DATA09    0x1b088
            >;
        };
        pinctrl_enet1: enet1grp {
            fsl,pins = <
                MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN    0x1b0b0
                MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER    0x1b0b0
                MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00    0x1b0b0
                MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01    0x1b0b0
                MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN    0x1b0b0
                MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00    0x1b0b0
                MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01    0x1b0b0
                MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1    0x4001b009
            >;
        };
        pinctrl_enet2: enet2grp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO07__ENET2_MDC        0x1b0b0
                MX6UL_PAD_GPIO1_IO06__ENET2_MDIO    0x1b0b0
                MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN    0x1b0b0
                MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER    0x1b0b0
                MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00    0x1b0b0
                MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01    0x1b0b0
                MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN    0x1b0b0
                MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00    0x1b0b0
                MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01    0x1b0b0
                MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2    0x4001b009
            >;
        };
        pinctrl_flexcan1: flexcan1grp{
            fsl,pins = <
                MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX    0x1b020
                MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX    0x1b020
            >;
        };
        pinctrl_flexcan2: flexcan2grp{
            fsl,pins = <
                MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX    0x1b020
                MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX    0x1b020
            >;
        };
        pinctrl_i2c1: i2c1grp {
            fsl,pins = <
                MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
                MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
            >;
        };
        pinctrl_i2c2: i2c2grp {
            fsl,pins = <
                MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
                MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
            >;
        };
        pinctrl_lcdif_dat: lcdifdatgrp {
            fsl,pins = <
                MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
                MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
                MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
                MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
                MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
                MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
                MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
                MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
                MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
                MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
                MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
                MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
                MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
                MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
                MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
                MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
                MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
                MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
                MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
                MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
                MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
                MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
                MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
                MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
            >;
        };
        pinctrl_lcdif_ctrl: lcdifctrlgrp {
            fsl,pins = <
                MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
                MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
                MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
                MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
            >;
        };
        pinctrl_pwm1: pwm1grp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
            >;
        };
        pinctrl_qspi: qspigrp {
            fsl,pins = <
                MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
                MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
                MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
                MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
                MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
                MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
            >;
        };
        pinctrl_sai2: sai2grp {
            fsl,pins = <
                MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK    0x17088
                MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC    0x17088
                MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA    0x11088
                MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA    0x11088
                MX6UL_PAD_JTAG_TMS__SAI2_MCLK        0x17088
            >;
        };
        pinctrl_tsc: tscgrp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO01__GPIO1_IO01    0xb0
                MX6UL_PAD_GPIO1_IO02__GPIO1_IO02    0xb0
                MX6UL_PAD_GPIO1_IO03__GPIO1_IO03    0xb0
                MX6UL_PAD_GPIO1_IO04__GPIO1_IO04    0xb0
            >;
        };
        pinctrl_uart1: uart1grp {
            fsl,pins = <
                MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
                MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
            >;
        };
        pinctrl_uart2: uart2grp {
            fsl,pins = <
                MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX    0x1b0b1
                MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX    0x1b0b1
                MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS    0x1b0b1
                MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS    0x1b0b1
            >;
        };
        pinctrl_uart2dte: uart2dtegrp {
            fsl,pins = <
                MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX    0x1b0b1
                MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX    0x1b0b1
                MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS    0x1b0b1
                MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS    0x1b0b1
            >;
        };
        pinctrl_usdhc1: usdhc1grp {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
            >;
        };
        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
            >;
        };
        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
            >;
        };
        pinctrl_usdhc2: usdhc2grp {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
            >;
        };
        pinctrl_usdhc2_8bit: usdhc2grp_8bit {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
                MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
                MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
                MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
                MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
            >;
        };
        pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
                MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
                MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
                MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
                MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
            >;
        };
        pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
                MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
                MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
                MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
                MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
            >;
        };
        pinctrl_wdog: wdoggrp {
            fsl,pins = <
                MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
            >;
        };
    };
};
&iomuxc_snvs {
    pinctrl-names = "default_snvs";
        pinctrl-0 = <&pinctrl_hog_2>;
        imx6ul-evk {
         /* paranoid Touch RESET */
        pinctrl_tsc_reset: tsc_reset {
            fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x10B0
                        >;
        };
        /* paranoid RGB RESET */
        ts_reset_hdmi_pin: ts_reset_hdmi_mux {
            fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49
                        >;
        };
        pinctrl_hog_2: hoggrp-2 {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
                        >;
                };
        pinctrl_dvfs: dvfsgrp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
                        >;
                };
        pinctrl_lcdif_reset: lcdifresetgrp {
                        fsl,pins = <
                                /* used for lcd reset */
                                MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
                        >;
                };
        pinctrl_spi4: spi4grp {
                        fsl,pins = <
                                MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
                                MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
                        >;
                };
        pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x17059
                        >;
                };
        /*enet1 reset paranoid*/
        pinctrl_enet1_reset: enet1resetgrp {
                        fsl,pins = <
                                /* used for enet1  reset */
                                MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x10B0      /* ENET1 RESET */
                        >;
                };
        /*enet2 reset paranoid*/
        pinctrl_enet2_reset: enet2resetgrp {
                        fsl,pins = <
                                /* used for enet2  reset */
                                MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x10B0     /* ENET2 RESET */      
                        >;
                };    
        };
};
&lcdif {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_lcdif_dat
             &pinctrl_lcdif_ctrl
             &pinctrl_lcdif_reset>;
    display = <&display0>;
    status = "okay";
    display0: display {
        bits-per-pixel = <16>;
        bus-width = <24>;
        display-timings {
            native-mode = <&timing0>;
            timing0: timing0 {
            clock-frequency = <9200000>;
            hactive = <480>;
            vactive = <272>;
            hfront-porch = <8>;
            hback-porch = <4>;
            hsync-len = <41>;
            vback-porch = <2>;
            vfront-porch = <4>;
            vsync-len = <10>;
            hsync-active = <0>;
            vsync-active = <0>;
            de-active = <1>;
            pixelclk-active = <0>;
            };
        };
    };
};
&pwm1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_pwm1>;
    status = "okay";
};
&pxp {
    status = "okay";
};
&qspi {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_qspi>;
    status = "okay";
    ddrsmp=<0>;
    flash0: n25q256a@0 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "micron,n25q256a";
        spi-max-frequency = <29000000>;
        spi-nor,ddr-quad-read-dummy = <6>;
        reg = <0>;
    };
};
&sai2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai2
             &pinctrl_sai2_hp_det_b>;
    assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
              <&clks IMX6UL_CLK_SAI2>;
    assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <0>, <12288000>;
    status = "okay";
};
&tsc {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_tsc>;
    xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
    measure-delay-time = <0xffff>;
    pre-charge-time = <0xfff>;
    status = "okay";
};
&uart1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_uart1>;
    status = "okay";
};
&uart2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_uart2>;
    fsl,uart-has-rtscts;
    /* for DTE mode, add below change */
    /* fsl,dte-mode; */
    /* pinctrl-0 = <&pinctrl_uart2dte>; */
    status = "okay";
};
&usbotg1 {
    dr_mode = "otg";
    srp-disable;
    hnp-disable;
    adp-disable;
    status = "okay";
};
&usbotg2 {
    dr_mode = "host";
    disable-over-current;
    status = "okay";
};
&usbphy1 {
    tx-d-cal = <0x5>;
};
&usbphy2 {
    tx-d-cal = <0x5>;
};
&usdhc1 {
    pinctrl-names = "default", "state_100mhz", "state_200mhz";
    pinctrl-0 = <&pinctrl_usdhc1>;
    pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
    pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
    cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
    keep-power-in-suspend;
    enable-sdio-wakeup;
    vmmc-supply = <&reg_sd1_vmmc>;
    status = "okay";
};
&usdhc2 {
    pinctrl-names = "default", "state_100mhz", "state_200mhz";
    pinctrl-0 = <&pinctrl_usdhc2_8bit>;
    pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
    pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
    bus-width = <8>;
    non-removable;
    status = "okay";
};
&wdog1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_wdog>;
    fsl,wdog_b;
};

最终设备树内容

/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"
/ {
    model = "Freescale i.MX6 ULL 14x14 EVK Board";
    compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
    chosen {
        stdout-path = &uart1;
    };
    memory {
        reg = <0x80000000 0x20000000>;
    };
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        linux,cma {
            compatible = "shared-dma-pool";
            reusable;
            size = <0x14000000>;
            linux,cma-default;
        };
    };
    backlight {
        compatible = "pwm-backlight";
        pwms = <&pwm1 0 5000000>;
        brightness-levels = <0 4 8 16 32 64 128 255>;
        default-brightness-level = <7>;
        status = "okay";
    };
    pxp_v4l2 {
        compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
        status = "okay";
    };
    regulators {
        compatible = "simple-bus";
        #address-cells = <1>;
        #size-cells = <0>;
        reg_can_3v3: regulator@0 {
            compatible = "regulator-fixed";
            reg = <0>;
            regulator-name = "can-3v3";
            regulator-min-microvolt = <3300000>;
            regulator-max-microvolt = <3300000>;
            gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
        };
        reg_sd1_vmmc: regulator@1 {
            compatible = "regulator-fixed";
            regulator-name = "VSD_3V3";
            regulator-min-microvolt = <3300000>;
            regulator-max-microvolt = <3300000>;
            //gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
            enable-active-high;
        };
        /* zuozhongkai ADC vref 3.3V */
        reg_vref_adc: regulator@2 {
            compatible = "regulator-fixed";
            regulator-name = "VREF_3V3";
            regulator-min-microvolt = <3300000>;
            regulator-max-microvolt = <3300000>;
        };
        reg_gpio_dvfs: regulator-gpio {
            compatible = "regulator-gpio";
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_dvfs>;
            regulator-min-microvolt = <1300000>;
            regulator-max-microvolt = <1400000>;
            regulator-name = "gpio_dvfs";
            regulator-type = "voltage";
            gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
            states = <1300000 0x1 1400000 0x0>;
        };
    };
    sound {
        compatible = "fsl,imx6ul-evk-wm8960",
               "fsl,imx-audio-wm8960";
        model = "wm8960-audio";
        cpu-dai = <&sai2>;
        audio-codec = <&codec>;
        asrc-controller = <&asrc>;
        codec-master;
        gpr = <&gpr 4 0x100000 0x100000>;
        /*
                 * hp-det = <hp-det-pin hp-det-polarity>;
         * hp-det-pin: JD1 JD2  or JD3
         * hp-det-polarity = 0: hp detect high for headphone
         * hp-det-polarity = 1: hp detect high for speaker
         */
        hp-det = <3 0>;
        /*hp-det-gpios = <&gpio5 4 0>;
        mic-det-gpios = <&gpio5 4 0>;*/
        audio-routing =
            "Headphone Jack", "HP_L",
            "Headphone Jack", "HP_R",
            "Ext Spk", "SPK_LP",
            "Ext Spk", "SPK_LN",
            "Ext Spk", "SPK_RP",
            "Ext Spk", "SPK_RN",
            "LINPUT2", "Mic Jack",
            "LINPUT3", "Mic Jack",
            "RINPUT1", "Main MIC",
            "RINPUT2", "Main MIC",
            "Mic Jack", "MICB",
            "Main MIC", "MICB",
            "CPU-Playback", "ASRC-Playback",
            "Playback", "CPU-Playback",
            "ASRC-Capture", "CPU-Capture",
            "CPU-Capture", "Capture";
    };
    spi4 {
        compatible = "spi-gpio";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spi4>;
        /* pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; */
        status = "okay";
        gpio-sck = <&gpio5 11 0>;
        gpio-mosi = <&gpio5 10 0>;
        /* cs-gpios = <&gpio5 7 0>;*/
        num-chipselects = <1>;
        #address-cells = <1>;
        #size-cells = <0>;
        gpio_spi: gpio_spi@0 {
            compatible = "fairchild,74hc595";
            gpio-controller;
            #gpio-cells = <2>;
            reg = <0>;
            registers-number = <1>;
            registers-default = /bits/ 8 <0x57>;
            spi-max-frequency = <100000>;
        };
    };
    /* paranoid dts leds linux自带led驱动的设备树*/
   /* dtsleds {
        compatible = "gpio-leds";
        led0 {
            label = "red";
            gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
            linux,default-trigger = "heartbeat";
            default-state = "on";
        };
    };*/
    /* zuozhongkai */
    alphaled {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "atkalpha-led";
        status = "okay";
        reg = < 0X020C406C 0X04        /* CCM_CCGR1_BAE             */
                0X020E0068 0X04        /* SW_MUX_GPIO1_IO03_BASE     */
                0X020E02F4 0X04        /* SW_PAD_GPIO1_IO03_BASE    */
                0X0209C000 0X04        /* GPIO1_DR_BASE             */
                0X0209C004 0X04>;    /* GPIO1_GDIR_BASE             */
    };
    gpioled {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "atkalpha-gpioled";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_led>;
        led-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
        status = "okay";
    };
    beep {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "atkalpha-beep";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_beep>;
        beep-gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
        status = "okay";
    };
    key {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "atkalpha-key";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_key>;
        key-gpio = <&gpio1 18 GPIO_ACTIVE_LOW>; /* KEY0 */
        interrupt-parent = <&gpio1>;
        interrupts = <18 IRQ_TYPE_EDGE_BOTH>; /* FALLING RISING */
        status = "okay";
    };
    /* zuozhongkai dts keys linux自带的key驱动设备树 */
    gpio-keys {
        compatible = "gpio-keys";
        #address-cells = <1>;
        #size-cells = <0>;
        autorepeat;
        key0 {
            label = "GPIO Key Enter";
            linux,code = <KEY_ENTER>;
            gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
        };
    };
    /* paranoid sii902x reset */
    sii902x_reset: sii902x-reset {
        compatible = "gpio-reset";
        reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
        reset-delay-us = <100000>;
        #reset-cells = <0>;
        status = "disabled";
    };
};
&cpu0 {
    arm-supply = <&reg_arm>;
    soc-supply = <&reg_soc>;
    dc-supply = <&reg_gpio_dvfs>;
};
&clks {
    assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <786432000>;
};
&csi {
    status = "okay";
    port {
        csi1_ep: endpoint {
            remote-endpoint = <&ov5640_ep>;
        };
    };
};
&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet1
            &pinctrl_enet1_reset>;
    phy-mode = "rmii";
    phy-handle = <&ethphy0>;
    phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
    phy-reset-duration = <200>;
    status = "okay";
};
&fec2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet2
                &pinctrl_enet2_reset>;
    phy-mode = "rmii";
    phy-handle = <&ethphy1>;
    phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
    phy-reset-duration = <200>;
    status = "okay";
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        ethphy0: ethernet-phy@0 {
            compatible = "ethernet-phy-ieee802.3-c22";
            smsc,disable-energy-detect;
            reg = <0>;
         };
        ethphy1: ethernet-phy@1 {
            compatible = "ethernet-phy-ieee802.3-c22";
            smsc,disable-energy-detect;
            reg = <1>;
        };
    };
};
&flexcan1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_flexcan1>;
    xceiver-supply = <&reg_can_3v3>;
    status = "okay";
};
&gpc {
    fsl,cpu_pupscr_sw2iso = <0x1>;
    fsl,cpu_pupscr_sw = <0x0>;
    fsl,cpu_pdnscr_iso2sw = <0x1>;
    fsl,cpu_pdnscr_iso = <0x1>;
    fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};
&i2c1 {
    clock-frequency = <100000>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_i2c1>;
    status = "okay";
    ap3216c@1e {
        compatible = "alientek,ap3216c";
        reg = <0x1e>;
    };
};
&i2c2 {
    clock_frequency = <100000>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_i2c2>;
    status = "okay";
    codec: wm8960@1a {
        compatible = "wlf,wm8960";
        reg = <0x1a>;
        clocks = <&clks IMX6UL_CLK_SAI2>;
        clock-names = "mclk";
        wlf,shared-lrclk;
    };
    ov5640: ov5640@3c {
        compatible = "ovti,ov5640";
        reg = <0x3c>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_csi1>;
        clocks = <&clks IMX6UL_CLK_CSI>;
        clock-names = "csi_mclk";
        pwn-gpios = <&gpio_spi 6 1>;
        rst-gpios = <&gpio_spi 5 0>;
        csi_id = <0>;
        mclk = <24000000>;
        mclk_source = <0>;
        status = "disabled";
        port {
            ov5640_ep: endpoint {
                remote-endpoint = <&csi1_ep>;
            };
        };
    };
    /* paranoid FT5406/FT5426 */
    ft5426: ft5426@38 {
        compatible = "edt,edt-ft5426","edt,edt-ft5406";
        reg = <0x38>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_tsc
                    &pinctrl_tsc_reset >; 
        interrupt-parent = <&gpio1>; 
        interrupts = <9 0>; 
        reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;  
        interrupt-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 
        status = "okay";
    };
    gt9147:gt9147@14 {
        compatible = "goodix,gt9147", "goodix,gt9xx";
        reg = <0x14>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_tsc
                    &pinctrl_tsc_reset >; 
        interrupt-parent = <&gpio1>; 
        interrupts = <9 0>; 
        reset-gpios  = <&gpio5 9 GPIO_ACTIVE_LOW>;
        interrupt-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 
        status = "disable";  /* 如果需要改为okay */
    };
    /* zuozhongkai sill902x,如果需要HDMI就将status改为okay即可  */
    /*
    sii902x: sii902x@39 {
        compatible = "SiI,sii902x";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sii902x>;
        interrupt-parent = <&gpio1>;
        interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
        irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
        mode_str = "1280x720M@60";
        bits-per-pixel = <16>;
        resets = <&sii902x_reset>;
        reg = <0x39>;
        status = "disable"; 
    };*/
};
&iomuxc {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_hog_1>;
    imx6ul-evk {
        pinctrl_hog_1: hoggrp-1 {
            fsl,pins = <
                MX6UL_PAD_UART1_RTS_B__GPIO1_IO19    0x17059 /* SD1 CD */
                MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
                /* MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 SD1 RESET */
                MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x13058    /* USB_OTG1_ID */
            >;
        };
        /* paranoid LED */
        pinctrl_led: ledgrp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x10B0 /* LED0 */
            >;
        };
        /* paranoid BEEP */
        pinctrl_beep: beepgrp {
            fsl,pins = <
                MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x10B0 /* beep */    
            >;
        };
        /* paranoid KEY */
        pinctrl_key: keygrp {
            fsl,pins = <
                MX6UL_PAD_UART1_CTS_B__GPIO1_IO18        0xF080    /* KEY0 */
            >;
        };        
        /* paranoid ECSPI */
        pinctrl_ecspi3: icm20608 {
            fsl,pins = < 
                MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20        0x10b0    /* CS */
                MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK    0x10b1    /* SCLK */
                MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO        0x10b1    /* MISO */
                MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI        0x10b1    /* MOSI */
            >;
        };
        /* paranoid HDMI RGB */
        pinctrl_hdmi_dat: hdmidatgrp {
            /* do not change the pimux vlaue on alpaha and mini board*/
            fsl,pins = <
                MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x49
                MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x49
                MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x49
                MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x49
                MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x49
                MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x49
                MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x49
                MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x49
                MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x49
                MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x49
                MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x49
                MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x49
                MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x49
                MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x49
                MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x49
                MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x51
                MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x49
                MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x49
                MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x49 
                MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x49
                MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x49
                MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x49
                MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x49
                MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x49
            >;
        };
        /* paranoid HDMI RGB */
        pinctrl_hdmi_ctrl: hdmictrlgrp {
            fsl,pins = <
                MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x49
                MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x49
                MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x49
                MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x49
            >;
        };
        /* paranoid SII902X  INT*/
        pinctrl_sii902x: hdmigrp-1 {
            fsl,pins = <
                /*MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x11*/
            >;
        };
        /* paranoid PWM3 GPIO1_IO04 */
        pinctrl_pwm3: pwm3grp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO04__PWM3_OUT   0x110b0
            >;
        };
        /* zuozhongkai ADC1_CH1 GPIO1_IO01 */
        pinctrl_adc1: adc1grp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO01__GPIO1_IO01   0xb0 
            >;
        };
        pinctrl_csi1: csi1grp {
            fsl,pins = <
                MX6UL_PAD_CSI_MCLK__CSI_MCLK        0x1b088
                MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK    0x1b088 
                MX6UL_PAD_CSI_VSYNC__CSI_VSYNC        0x1b088
                MX6UL_PAD_CSI_HSYNC__CSI_HSYNC        0x1b088
                MX6UL_PAD_CSI_DATA00__CSI_DATA02    0x1b088
                MX6UL_PAD_CSI_DATA01__CSI_DATA03    0x1b088
                MX6UL_PAD_CSI_DATA02__CSI_DATA04    0x1b088
                MX6UL_PAD_CSI_DATA03__CSI_DATA05    0x1b088
                MX6UL_PAD_CSI_DATA04__CSI_DATA06    0x1b088
                MX6UL_PAD_CSI_DATA05__CSI_DATA07    0x1b088
                MX6UL_PAD_CSI_DATA06__CSI_DATA08    0x1b088
                MX6UL_PAD_CSI_DATA07__CSI_DATA09    0x1b088
            >;
        };
        pinctrl_enet1: enet1grp {
            fsl,pins = <
                MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN    0x1b0b0
                MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER    0x1b0b0
                MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00    0x1b0b0
                MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01    0x1b0b0
                MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN    0x1b0b0
                MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00    0x1b0b0
                MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01    0x1b0b0
                MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1    0x4001b009
            >;
        };
        pinctrl_enet2: enet2grp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO07__ENET2_MDC        0x1b0b0
                MX6UL_PAD_GPIO1_IO06__ENET2_MDIO    0x1b0b0 
                MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN    0x1b0b0
                MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER    0x1b0b0
                MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00    0x1b0b0
                MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01    0x1b0b0
                MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN    0x1b0b0
                MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00    0x1b0b0
                MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01    0x1b0b0
                MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2    0x4001b009 
            >;
        };
        pinctrl_flexcan1: flexcan1grp{
            fsl,pins = <
                MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX    0x1b020
                MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX    0x1b020
            >;
        };
        pinctrl_flexcan2: flexcan2grp{
            fsl,pins = <
                /* MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX    0x1b020 */
                /* MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX    0x1b020 */
            >;
        };
        pinctrl_i2c1: i2c1grp {
            fsl,pins = <
                MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
                MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 
            >;
        };
        pinctrl_i2c2: i2c2grp {
            fsl,pins = <
                MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
                MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
            >;
        };
        pinctrl_lcdif_dat: lcdifdatgrp {
            fsl,pins = <
                MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x49
                MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x49
                MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x49
                MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x49
                MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x49
                MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x49
                MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x49
                MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x49
                MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x49
                MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x49
                MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x49
                MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x49
                MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x49
                MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x49
                MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x49
                MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x49
                MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x49
                MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x49
                MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x49 
                MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x49
                MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x49
                MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x49
                MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x49
                MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x49
            >;
        };
        pinctrl_lcdif_ctrl: lcdifctrlgrp {
            fsl,pins = <
                MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
                MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
                MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
                MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
            >;
        };
        pinctrl_pwm1: pwm1grp {
            fsl,pins = <
                MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
            >;
        };
        pinctrl_qspi: qspigrp {
            fsl,pins = <
                MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
                MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
                MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
                MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
                MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
                MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
            >;
        };
        pinctrl_sai2: sai2grp {
            fsl,pins = <
                MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK    0x17088
                MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC    0x17088
                MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA    0x11088
                MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA    0x11088
                MX6UL_PAD_JTAG_TMS__SAI2_MCLK        0x17088
            >;
        };
        pinctrl_tsc: tscgrp {
            fsl,pins = <
                /* 7寸RGB屏幕,FT5426 */
                /* MX6UL_PAD_GPIO1_IO09__GPIO1_IO09    0xF080     */    /* TSC_INT */
                /* 7寸RGB屏幕,GT9147 */
                /* MX6UL_PAD_GPIO1_IO09__GPIO1_IO09    0x10B0     */    /* TSC_INT */
            >;
        };
        pinctrl_uart1: uart1grp {
            fsl,pins = <
                MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
                MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
            >;
        };
        pinctrl_uart2: uart2grp {
            fsl,pins = <
                /* MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX    0x1b0b1 */
                /* MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX    0x1b0b1 */
                MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS    0x1b0b1
                MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS    0x1b0b1
            >;
        };
        pinctrl_uart2dte: uart2dtegrp {
            fsl,pins = <
                /* MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX    0x1b0b1 */
                /* MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX    0x1b0b1 */
                /* MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS    0x1b0b1 */
                /* MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS    0x1b0b1 */
            >; 
        };
        /* zuozhongkai */
        pinctrl_uart3: uart3grp {
            fsl,pins = <
                MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX        0X1b0b1
                MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX        0X1b0b1
            >;
        };
        pinctrl_usdhc1: usdhc1grp {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f1
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
            >;
        };
        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f1
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
            >;
        };
        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
            fsl,pins = <
                MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
                MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f1
                MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
                MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
                MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
                MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
            >;
        };
        pinctrl_usdhc2: usdhc2grp {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
            >;
        };
        pinctrl_usdhc2_8bit: usdhc2grp_8bit {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
                MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
                MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
                MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
                MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
            >;
        };
        pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
                MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
                MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
                MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
                MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
            >;
        };
        pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
            fsl,pins = <
                MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
                MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
                MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
                MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
                MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
                MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
                MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
                MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
                MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
                MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
            >;
        };
        pinctrl_wdog: wdoggrp {
            fsl,pins = <
                MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
            >;
        };
    };
};
&iomuxc_snvs {
    pinctrl-names = "default_snvs";
        pinctrl-0 = <&pinctrl_hog_2>;
        imx6ul-evk {
        /* zuozhongkai Touch RESET */
        pinctrl_tsc_reset: tsc_reset {
            fsl,pins = <
                                 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x10B0
                        >;
        };
        /* zuozhongkai RGB RESET */
        ts_reset_hdmi_pin: ts_reset_hdmi_mux {
            fsl,pins = <
                                 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49
                        >;
        };
        pinctrl_hog_2: hoggrp-2 {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
                        >;
                };
        pinctrl_dvfs: dvfsgrp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
                        >;
                };
        pinctrl_lcdif_reset: lcdifresetgrp {
                        fsl,pins = <
                                /* used for lcd reset */
                                /* MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79 */
                        >;
                };
        pinctrl_spi4: spi4grp {
                        fsl,pins = <
                                MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
                                MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
                        >;
                };
        pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x17059
                        >;
                };
        /*enet1 reset zuozhongkai*/
        pinctrl_enet1_reset: enet1resetgrp {
                        fsl,pins = <
                                /* used for enet1  reset */
                                MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x10B0      /* ENET1 RESET */
                        >;
                };
        /*enet2 reset zuozhongkai*/
        pinctrl_enet2_reset: enet2resetgrp {
                        fsl,pins = <
                                /* used for enet2  reset */
                                MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x10B0     /* ENET2 RESET */      
                        >;
                };
        };
};
&lcdif {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_lcdif_dat
             &pinctrl_lcdif_ctrl>;
    display = <&display0>;
    status = "okay"; 
    /* 7寸1024*600 */
    display0: display {
        bits-per-pixel = <24>;
        bus-width = <24>;
        display-timings {
            native-mode = <&timing0>;
            timing0: timing0 {
            clock-frequency = <51200000>;
            hactive = <1024>;
            vactive = <600>;
            hfront-porch = <160>;
            hback-porch = <140>;
            hsync-len = <20>;
            vback-porch = <20>;
            vfront-porch = <12>;
            vsync-len = <3>;
            hsync-active = <0>;
            vsync-active = <0>;
            de-active = <1>;
            pixelclk-active = <0>;
            };
        };
    };
    /* 4.3寸480*272 */
    /* display0: display {
        bits-per-pixel = <24>;
        bus-width = <24>;
        display-timings {
            native-mode = <&timing0>;
            timing0: timing0 {
            clock-frequency = <9000000>;
            hactive = <480>;
            vactive = <272>;
            hfront-porch = <5>;
            hback-porch = <40>;
            hsync-len = <1>;
            vback-porch = <8>;
            vfront-porch = <8>;
            vsync-len = <1>;
            hsync-active = <0>;
            vsync-active = <0>;
            de-active = <1>;
            pixelclk-active = <0>;
            };
        };
    };*/
    /* 4.3寸800*480 */
    /* display0: display {
        bits-per-pixel = <24>;
        bus-width = <24>;
        display-timings {
            native-mode = <&timing0>;
            timing0: timing0 {
            clock-frequency = <31000000>;
            hactive = <800>;
            vactive = <480>;
            hfront-porch = <40>;
            hback-porch = <88>;
            hsync-len = <48>;
            vback-porch = <32>;
            vfront-porch = <13>;
            vsync-len = <3>;
            hsync-active = <0>;
            vsync-active = <0>;
            de-active = <1>;
            pixelclk-active = <0>;
            };
        };
    };*/
};
&pwm1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_pwm1>;
    status = "okay";
};
/* zuozhongkai PWM3 */
&pwm3 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_pwm3>;
    clocks = <&clks IMX6UL_CLK_PWM3>,
             <&clks IMX6UL_CLK_PWM3>;
    status = "disable";
};
/* zuozhongkai ADC1 */
&adc1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_adc1>;
    num-channels = <2>;
    vref-supply = <&reg_vref_adc>;
    status = "okay";    
};
&pxp {
    status = "okay";
};
&qspi {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_qspi>;
    status = "okay";
    ddrsmp=<0>;
    flash0: n25q256a@0 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "micron,n25q256a";
        spi-max-frequency = <29000000>;
        spi-nor,ddr-quad-read-dummy = <6>;
        reg = <0>;
    };
};
&sai2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai2
             &pinctrl_sai2_hp_det_b>;
    assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
              <&clks IMX6UL_CLK_SAI2>;
    assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <0>, <12288000>;
    status = "okay";
};
&tsc {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_tsc>;
    /*xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;*/
    measure-delay-time = <0xffff>;
    pre-charge-time = <0xfff>;
    status = "disable";
};
&uart1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_uart1>;
    status = "okay";
};
/* zuozhongkai */
&uart3 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_uart3>;
    status = "okay";
};
&usbotg1 {
    dr_mode = "otg";
    srp-disable;
    hnp-disable;
    adp-disable;
    status = "okay";
};
&usbotg2 {
    dr_mode = "host";
    disable-over-current;
    status = "okay";
};
&usbphy1 {
    tx-d-cal = <0x5>;
};
&usbphy2 {
    tx-d-cal = <0x5>;
};
&usdhc1 {
    pinctrl-names = "default", "state_100mhz", "state_200mhz";
    pinctrl-0 = <&pinctrl_usdhc1>;
    pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
    pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
    cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
    keep-power-in-suspend;
    enable-sdio-wakeup;
    vmmc-supply = <&reg_sd1_vmmc>;
    status = "okay";
    no-1-8-v;
};
&usdhc2 {
    pinctrl-names = "default", "state_100mhz", "state_200mhz";
    pinctrl-0 = <&pinctrl_usdhc2_8bit>;
    pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
    pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
    bus-width = <8>;
    non-removable;
    status = "okay";
};
&wdog1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_wdog>;
    fsl,wdog_b;
};
/* zuozhongkai  */
&ecspi3 {
    fsl,spi-num-chipselects = <1>;
    cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; /* cant't use cs-gpios! */
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_ecspi3>;
    status = "okay";
    spidev: icm20608@0 {
        compatible = "alientek,icm20608";
        spi-max-frequency = <8000000>;
        reg = <0>;
    };    
};

最终结果

网络驱动测试

修改好设备树和 Linux 内核以后重新编译一下,

cp arch/arm/boot/zImage /home/alientek/linux/tftp/ -f

cp arch/arm/boot/dts/imx6ull-alientek-emmc.dtb /home/alientek/linux/tftp/ -f

得到新的 zImage 镜像文件和 imx6ullalientek-emmc.dtb 设备树文件,使用网线将 I.MX6U-ALPHA 开发板的两个网口与路由器或者电脑连接起来,最后使用新的文件启动 Linux 内核。启动以后使用“ifconfig”命令查看一下当前活动的网卡有哪些,结果如图所示:

输入命令“ifconfig -a”来查看一下开发板中存在的所有网卡,结果如图 所示:

eth0 和 eth1 才网络接口的网卡,其中eth0 对应于 ENET2, eth1 对应于 ENET1。使用如下命令依次打开 eth0 和 eth1 这两个网卡:

ifconfig eth0 up
ifconfig eth1 up

网卡的打开过程如图 所示:

从图中可以看到“Generic PHY”字样,说明当前的网络驱动使用的就是我们使能的 PHY 驱动。

再次输入“ifconfig”命令来查看一下当前活动的网卡,

可以看出,此时 eth0 和 eth1 两个网卡都已经打开,并且工作正常,但是这两个网卡都还没有 IP 地址,所以不能进行ping 等操作。使用如下命令给两个网卡配置IP 地址:

ifconfig eth0 XXXXXXX

ifconfig eth1 XXXXXXXX

上述命令配置 eth0 和 eth1 这两个网卡的 IP 地址分别为 XXXX 和 XXXXX,注意 IP 地址选择的合理性,一定要和自己的电脑处于同一个网段内,并且没有被其他的设备占用!设置好以后,使用“ping”命令来 ping 一下自己的主机,如果能 ping 通那说明网络驱动修改成功!比如我的Ubuntu 主机 IP 地址为 192.168.10.100,使用如下命令ping 一下:

ping 192.168.10.100

结果如图所示:

可以看出, ping 成功,说明网络驱动修改成功!我们在后面的构建根文件系统和 Linux 驱动开发中就可以使用网络调试代码啦。

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