数字逻辑电路设计实验：计时器/奇数骑

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shiyan4 is
  port(rst,clk,en,ld:in std_logic;
  data:in std_logic_vector(3 downto 0);
  tc:out std_logic;
  count:out std_logic_vector(3 downto 0));
end shiyan4;
architecture mtimer of shiyan4 is
  signal mdata:std_logic_vector(3 downto 0);
  begin
    counting:process(clk,en,ld,rst)
      begin
      if(rst='0') then mdata<="0000";
      elsif (clk'event and clk='1') then
        if (ld='0') then mdata<=data;
        elsif(en='1') then
          if mdata="1001" then mdata<="0000";
          else mdata<=mdata+'1';
          end if;
        end if;
      end if;
  end process counting;
  count<=mdata;
    outt:process(mdata)
      begin
      if(mdata="1001") then tc<='1';
      else tc<='0';
      end if;
    end process outt;
end mtimer;