Vivado下PLL实验 2

三、进行仿真

1、创建仿真文件

创建名为 vtf_pll_test.v 的仿真文件，并进行例化编写 verilog 仿真程序

`timescale 1ns / 1ps
module vtf_pll_test;
reg sys_clk;
reg rst_n;
wire clk_out;
pll_test pll_inst(
    .sys_clk    (sys_clk),  // 50MHz
    .rst_n      (rst_n),
    .clk_out    (clk_out)
    );
initial 
begin
    sys_clk = 1'b0;
    rst_n = 1'b0;   // 对于按键来说我们进行的是低电平的一个复位
    # 100 rst_n = 1'b1;
end
always #10 sys_clk = ~sys_clk;  // 10ns 时钟翻转产生 25MHz 时钟
endmodule

2、进行仿真设置

①、右键 Run Simulation -> Simulation Settings…

②、设置仿真时间，这里填 200us 即可

3、进行行为级仿真

①、左键 Run Simulation -> Run Behavioral Simulation

②、将 vtf_pll_test 下的 pll_inst 下的 clk_inst 的 clk_out1、clk_out2、clk_out3、clk_out_4、reset、locked 拖拽到仿真界面 Name 栏下

③、点击 Run for 10us，可以看下图结果

四、硬件验证

1、引脚绑定

1、点击 “Open Elaborated Design”，再打开 Window 下的 I/O Ports

2、查看原理图

①、T11 -> rst_n，T0 -> clk_out

②、U18 -> sys_clk

③、因此分配情况如下：

④、进行保存

⑤、生成的 pll.xdc 文件如下图：

2、生成比特流文件

①、点击 “Generate Bitstream”，直接生成 bit 文件

出现了如下报错：

[Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_inst/inst/clk_in1_clk_wiz_0] >

clk_inst/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X0Y15
 clk_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X0Y0
The above error could possibly be related to other connected instances. Following is a list of 
all the related clock rules and their respective instances.
Clock Rule: rule_pll_bufg
Status: PASS 
Rule Description: A PLL driving a BUFG must be placed on the same half side (top/bottom) of the device
 clk_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKFBOUT) is provisionally placed by clockplacer on PLLE2_ADV_X0Y0
 and clk_inst/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y5

把这条提示加入 XDC 约束文件里面即可，原理就是绕过 PAR 的检查。

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_inst/inst/clk_in1_clk_wiz_0]

②、选择 Open Hardware Manager 并点击 OK

③、插上 fpga 仿真器及其电源，选择 Auto Connect

④、右键 xc7z020_1 -> Program Device

3、验证

找一个示波器用探头接到 T10 引脚查看输出，可以看到 25MHz 方波信号

五、资源自取

基于vivado 2017.4 的 pll 测试