The aeMB processor is a fully synthesized CPU that forms the heart of
the USRP2 FPGA system-on-a-chip design. It performs configuration and
status reporting for all the FPGA peripherals, manages the control
channel for the GbE transport, and handles RF daughterboard operation.
It does not perform any DSP functions; these are done purely in logic
in the DSP RX and TX pipelines. It is clocked at 50 MHz, half the
system clock rate.