前言
最近在学习一些verilog/system verilog for design的基础知识，觉得有些东西总结总结还是挺好的，毕竟好记性不如烂键盘；
正文开始
verilog有1995和2001两个标准，之后便合入到system verilog标准中了，因此结合最近看的课总结一下语法的演进；
verilog-1995
| module | parameter | function | task | always @ |
| assign | wire | reg | + = * / | % << >> |
| $finish | $fopen | $fclose | $display | $write |
| $monitor | `define | `ifdef `else `endif | `include | `timescale |
| initial | disable | events | wait # | @ |
| fork-join | intrger | real | time | packed array |
| 2D reg/memory |
感觉verilog-1995起点极高，for design已经基本覆盖常用的几句语法；但是for verification目测只能构造定向测试，还没有独立做随机环境的能力；
verilog-2001新增
| generate | localparam | constant function | @(*) | ANSI C style ports |
| standard file I/O | $value$plusargs | `ifndef | `elsif | `line |
| ** | multi dimensional array | signed type | automatic |
显然2001的语法主要变化是代码风格的变化，C style接口风格、generate、多维阵列引入，这感觉就到了~~~不过对于verification貌似推进不大，憋大招中，毕竟马上就断更verilog标准了；
`line这个语法我不懂，看描述是
In many cases, however, the SystemVerilog source is preprocessed by some other tool, and the line and file
information of the original source file can be lost.
The `line compiler directive can be used to specify the original source code line number and file name.
For example:
`line 3 "orig.v" 2
// This line is line 3 of orig.v after exiting include file
emmmm没用过，应该是手动来标记原始文件代码坐标的代码，用处我觉得不大；
SystemVerilog IEEE 1800 新增
| interface | modport | program | virtual | import |
| export | pure | context | DPI | package |
| bind | logic | bit | byte | shortint |
| longint | int | void | shortreal | packed |
| unpacked | dynamic | queue | const | alias |
| type | var | string | unique | priority |
| do while | foreach | return | break | continue |
| finial | iff | always_comb | always_latch | always_ff |
| join_any | join_none | wait fork | rand randc | dist with |
| constraint_mode | randsequence | semaphore | mailbox | assert |
| assume | cover | property | sequence | within/... |
| ##N | clocking | covergroup | bins | cast |
| class | new | statci | extend | super |
从system verilog标准开始，整体变化极大，system verilog作为verilog的超集，感觉上是想大幅提升RTL代码的抽象程度以及减少对底层的感知，引入interface/logic/var/always_comb/always_latch/always_ff/unique case/priority case以及结构体struct等一系列结构和语法，但是怎么说呢，个人觉得除了interface和packed struct能大幅增加代码的可阅读型以及减少代码量外，其他的语法感知不强；
但是对于验证维度来说，system verilog终于拯救了大家，oop曙光终将照耀大地~covergroup、assert、rand的引入逐步开始拓展出了随机验证，以至后面VMM/OVM/UVM的验证方法学。
