verilog牛客网刷题代码汇总（上）（3）

`timescale 1ns/1ns
module encoder_0(
    input              [   8:0]         I_n                        ,
    output reg         [   3:0]         Y_n                         
);
always @(*) begin
   casex (I_n)
    9'b1_1111_1111:Y_n <= 4'b1111;
    9'b0_xxxx_xxxx:Y_n <= 4'b0110;
    9'b1_0xxx_xxxx:Y_n <= 4'b0111;
    9'b1_10xx_xxxx:Y_n <= 4'b1000;
    9'b1_110x_xxxx:Y_n <= 4'b1001;
    9'b1_1110_xxxx:Y_n <= 4'b1010;
    9'b1_1111_0xxx:Y_n <= 4'b1011;
    9'b1_1111_10xx:Y_n <=4'b1100;
    9'b1_1111_110x:Y_n <= 4'b1101;
    9'b1_1111_1110:Y_n <= 4'b1110;
    default:       Y_n <= 4'b1111;
endcase
end
endmodule

`timescale 1ns/1ns
module encoder_0(
    input              [   8:0]         I_n                        ,
    output reg         [   3:0]         Y_n                         
);
always @(*)begin
   casex(I_n)
      9'b111111111 : Y_n = 4'b1111;
      9'b0xxxxxxxx : Y_n = 4'b0110;
      9'b10xxxxxxx : Y_n = 4'b0111;
      9'b110xxxxxx : Y_n = 4'b1000;
      9'b1110xxxxx : Y_n = 4'b1001;
      9'b11110xxxx : Y_n = 4'b1010;
      9'b111110xxx : Y_n = 4'b1011;
      9'b1111110xx : Y_n = 4'b1100;
      9'b11111110x : Y_n = 4'b1101;
      9'b111111110 : Y_n = 4'b1110;
      default      : Y_n = 4'b1111;
   endcase
end
endmodule
module key_encoder(
    input              [   9:0]         S_n                        ,
    output wire        [   3:0]         L                          ,
    output wire                         GS                          
);
wire                   [   3:0]         L_tmp                      ;
encoder_0 encoder_0(
    .I_n                               (S_n[9:1]                  ),
    .Y_n                               (L_tmp                     ) 
);
assign L = ~L_tmp;
assign GS = ((L_tmp == 4'b1111) && (S_n[0] == 1)) ? 0: 1;
endmodule

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
endmodule

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];
assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
endmodule
module encoder_164(
   input      [15:0]      A   ,  //分为高8位和低8位
   input                  EI  ,  //使能表示有无按键按下
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);
wire [2:0]      Y_0;
wire [2:0]      Y_1;
wire            GS_0;
wire            EO_0;    
wire            GS_1;
wire            EO_1;   
encoder_83 u_0(
    .I(A[7:0]),
    .EI(EO_1),
    .Y(Y_0),
    .GS(GS_0),
    .EO(EO)
);
encoder_83 u_1(
    .I(A[15:8]),
    .EI(EI),
    .Y(Y_1),
    .GS(GS_1),
    .EO(EO_1)
);
assign GS = GS_1 | GS_0;
assign L[3] = GS_1;
assign L[2] = Y_1[2] | Y_0[2];
assign L[1] = Y_1[1] | Y_0[1];
assign L[0] = Y_1[0] | Y_0[0];
endmodule