VHDL 七段显示译码器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SEG7_4 IS --工程名为SEG7_4
       PORT ( BCD_IN  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);   --输入四位BCD码
               SG_OUT  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));  --输出七位字形码
 END;
ARCHITECTURE ONE OF SEG7_4 IS
       BEGIN
        PROCESS(BCD_IN)
          BEGIN
           CASE  BCD_IN  IS
            WHEN "0000"  => SG_OUT <= "0111111";  
            WHEN "0001"  => SG_OUT <= "0000110"; 
            WHEN "0010"  => SG_OUT <= "1011011"; 
            WHEN "0011"  => SG_OUT <= "1001111"; 
            WHEN "0100"  => SG_OUT <= "1100110";  
            WHEN "0101"  => SG_OUT <= "1101101"; 
            WHEN "0110"  => SG_OUT <= "1111101"; 
            WHEN "0111"  => SG_OUT <= "0000111";
            WHEN "1000"  => SG_OUT <= "1111111";  
            WHEN "1001"  => SG_OUT <= "1101111"; 
            WHEN "1010" => SG_OUT <= "1110111";  
            WHEN "1011" => SG_OUT <= "1111100";
            WHEN "1100" => SG_OUT <= "0111001"; 
            WHEN "1101" => SG_OUT <= "1011110"; 
            WHEN "1110" => SG_OUT <= "1111001";  
            WHEN "1111" => SG_OUT <= "1110001";
            WHEN OTHERS =>  NULL ;
           END CASE ;
          END PROCESS;    
END;