nxp出厂Linux源码
https://download.csdn.net/download/weixin_52849254/87666595
移植成功后的Linux源码
https://download.csdn.net/download/weixin_52849254/87669505
NXP 提供的 Linux 源码肯定是可以在自己的 I.MX6ULL EVK 开发板上运行下去的，所以我们肯定是以 I.MX6ULL EVK 开发板为参考，然后将 Linux 内核移植到 I.MX6U-ALPHA 开发板上的。
下载内核
下载地址https://github.com/Freescale/linux-fslc
Freescale/linux-fslc: Linux kernel source tree (github.com)
https://github.com/Freescale/linux-fslc/tree/5.4-2.2.x-imx
解压
git clone https://github.com/Freescale/linux-fslc.git mkdir fs_5.4 unzip linux-fslc-5.4-2.2.x-imx.zip -d fs_5.4/
1.出厂源码编译
1 修改顶层 Makefile
修改顶层 Makefile，直接在顶层 Makefile 文件里面定义 ARCH 和 CROSS_COMPILE 这两个的变量值为 arm 和 arm-linux-gnueabihf-，结果如图所示：
vi Makefile
360 ARCH ?= arm 361 CROSS_COMPILE ?= arm-linux-gnueabihf-
或者（用这种）
export ARCH=arm export CROSS_COMPILE=arm-linux-gnueabihf-
第 360 和 361 行分别设置了 ARCH 和 CROSS_COMPILE 这两个变量的值，这样在编译的时候就不用输入很长的命令了。
2 配置并编译 Linux 内核
和 uboot 一样，在编译 Linux 内核之前要先配置 Linux 内核。每个板子都有其对应的默认配 置 文 件 ， 这 些 默 认 配 置 文 件 保 存 在 arch/arm/configs 目 录 中 。 imx_v7_defconfig 和imx_v7_mfg_defconfig 都可作为 I.MX6ULL EVK 开发板所使用的默认配置文件。但是这里建议使用 imx_v7_mfg_defconfig 这个默认配置文件，首先此配置文件默认支持 I.MX6UL 这款芯片，而且重要的一点就是此文件编译出来的 zImage 可以通过 NXP 官方提供的 MfgTool 工具烧写！！imx_v7_mfg_defconfig 中的“mfg”的意思就是 MfgTool
进入到 Ubuntu 中的 Linux 源码根目录下，执行如下命令配置 Linux 内核：
make clean //第一次编译 Linux 内核之前先清理一下
查看arch/arm/configs目录下imx6ull相关的单板：
ls arch/arm/configs/ | grep imx
make imx_v7_defconfig //配置 Linux 内核
配置完成以后如图所示：
配置完成以后就可以编译了，使用如下命令编译 Linux 内核：
编译之前先确定安装了libssl-dev 软件包
sudo apt install libssl-dev
make -j32 //编译 Linux 内核
等待编译完成，结果如图所示：
Linux 内核编译完成以后会在 arch/arm/boot 目录下生成 zImage 镜像文件，如果使用设备树的话还会在 arch/arm/boot/dts 目录下开发板对应的.dtb(设备树)文件，比如 imx6ull-14x14-evk.dtb就是 NXP 官方的 I.MX6ULL EVK 开发板对应的设备树文件。至此我们得到两个文件：
①、 Linux 内核镜像文件： zImage。
②、 NXP 官方 I.MX6ULL EVK 开发板对应的设备树文件： imx6ull-14x14-evk.dtb。
3 Linux 内核启动测试
在上一小节我们已经得到了 NXP 官方 I.MX6ULL EVK 开发板对应的 zImage 和 imx6ull-14x14-evk.dtb 这两个文件。这两个文件能不能在正点原子的 I.MX6U-ALPHA EMMC 版开发板上启动呢？测试一下不就知道了，在测试之前确保 uboot 中的环境变量 bootargs 内容如下：
setenv bootargs 'console=tty1 console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.10.100:/home/alientek/linux/nfs/rootfs,proto=tcp rw ip=192.168.10.101:192.168.10.100:192.168.10.1:255.255.255.0::eth0:off'
将上一小节编译出来的 zImage 和 imx6ull-14x14-evk.dtb 复制到 Ubuntu 中的 tftp 目录下，因为我们要在uboot 中使用 tftp 命令将其下载到开发板中，拷贝命令如下：
cp arch/arm/boot/zImage /home/alientek/linux/tftp/ -f cp arch/arm/boot/dts/imx6ull-14x14-evk.dtb /home/alientek/linux/tftp/ -f
拷贝完成以后就可以测试了，启动开发板，进入 uboot 命令行模式，然后输入如下命令将zImage 和 imx6ull-14x14-evk.dtb 下载到开发板中并启动：
tftp 80800000 zImage tftp 83000000 imx6ull-14x14-evk.dtb bootz 80800000 - 83000000
结果图所示：
2、移植linux内核,建立单板
（1）新建单板配置文件 进入 arch/arm/configs 目录，复制一份新的单板文件：
cp arch/arm/configs/imx_v7_defconfig arch/arm/configs/imx_alientek_emmc_defconfig
（2）新建设备树文件 进入 arch/arm/boot/dts 目录，复制一份新的设备树文件：
cp aimx6ull-14x14-evk-emmc.dts imx6ull-alientek-emmc.dts
复制并修改依赖
查看该文件，依赖于evk板子的设备树，需要将该文件也复制一份出来：
cp imx6ull-14x14-evk.dts imx6ull-alientek.dts
再查看有没有依赖，竟然还有一级：
5 /dts-v1/; 6 7 #include "imx6ull.dtsi" 8 #include "imx6ul-14x14-evk.dtsi"
修改依赖：
将该文件也复制一份出来：
cp imx6ul-14x14-evk.dtsi imx6ull-alientek.dtsi
接着修改同级目录下的Makefile，添加新建的文件：
vi Makefile
610 dtb-$(CONFIG_SOC_IMX6UL) += 611 imx6ul-14x14-evk.dtb 612 imx6ul-14x14-evk-csi.dtb 613 imx6ul-14x14-evk-emmc.dtb 614 imx6ul-14x14-evk-btwifi.dtb 615 imx6ul-14x14-evk-btwifi-oob.dtb 616 imx6ul-14x14-evk-ecspi-slave.dtb 617 imx6ul-14x14-evk-ecspi.dtb 618 imx6ul-14x14-evk-gpmi-weim.dtb 619 imx6ul-9x9-evk.dtb 620 imx6ul-9x9-evk-ldo.dtb 621 imx6ul-9x9-evk-btwifi.dtb 622 imx6ul-9x9-evk-btwifi-oob.dtb 623 imx6ul-ccimx6ulsbcexpress.dtb 624 imx6ul-ccimx6ulsbcpro.dtb 625 imx6ul-geam.dtb 626 imx6ul-isiot-emmc.dtb 627 imx6ul-isiot-nand.dtb 628 imx6ul-kontron-n6310-s.dtb 629 imx6ul-kontron-n6310-s-43.dtb 630 imx6ul-liteboard.dtb 631 imx6ul-opos6uldev.dtb 632 imx6ul-pico-hobbit.dtb 633 imx6ul-pico-pi.dtb 634 imx6ul-phytec-segin-ff-rdk-nand.dtb 635 imx6ul-tx6ul-0010.dtb 636 imx6ul-tx6ul-0011.dtb 637 imx6ul-tx6ul-mainboard.dtb 638 imx6ull-14x14-evk.dtb 639 imx6ull-alientek.dtb 640 imx6ull-alientek-emmc.dtb 641 imx6ull-14x14-evk-emmc.dtb 642 imx6ull-14x14-evk-btwifi.dtb 643 imx6ull-14x14-evk-btwifi-oob.dtb 644 imx6ull-14x14-evk-gpmi-weim.dtb 645 imx6ull-9x9-evk.dtb 646 imx6ull-9x9-evk-ldo.dtb 647 imx6ull-9x9-evk-btwifi.dtb 648 imx6ull-9x9-evk-btwifi-oob.dtb 649 imx6ull-colibri-eval-v3.dtb 650 imx6ull-colibri-wifi-eval-v3.dtb 651 imx6ull-phytec-segin-ff-rdk-nand.dtb 652 imx6ull-phytec-segin-ff-rdk-emmc.dtb 653 imx6ull-phytec-segin-lc-rdk-nand.dtb 654 imx6ulz-14x14-evk.dtb 655 imx6ulz-14x14-evk-btwifi.dtb 656 imx6ulz-14x14-evk-gpmi-weim.dtb 657 imx6ulz-14x14-evk-emmc.dtb
639，640行
（3）编译测试
make distclean make imx_alientek_emmc_defconfig make
复制
cp arch/arm/boot/zImage /home/alientek/linux/tftp/ -f cp arch/arm/boot/dts/imx6ull-alientek-emmc.dtb /home/alientek/linux/tftp/ -f
拷贝完成以后就可以测试了，启动开发板，进入 uboot 命令行模式，然后输入如下命令将zImage 和 imx6ull-14x14-evk.dtb 下载到开发板中并启动：
tftp 80800000 zImage tftp 83000000 imx6ull-alientek-emmc.dtb bootz 80800000 - 83000000
使用新的内核和设备树启动，方便起见，设个环境变量，下次直接用命令启动：
setenv bootargs 'console=tty1 console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.10.100:/home/alientek/linux/nfs/rootfs,proto=tcp rw ip=192.168.10.101:192.168.10.100:192.168.10.1:255.255.255.0::eth0:off'
setenv bootcmd 'tftp 80800000 zImage;tftp 83000000 imx6ull-alientek-emmc.dtb;bootz 80800000 - 83000000' saveenv
3.驱动修改
1.修改设备树
修改前
imx6ul-14x14-evk.dtsi
// SPDX-License-Identifier: GPL-2.0 // // Copyright (C) 2015 Freescale Semiconductor, Inc. / { chosen { stdout-path = &uart1; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; linux,cma { compatible = "shared-dma-pool"; reusable; size = <0xa000000>; linux,cma-default; }; }; backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; status = "okay"; }; pxp_v4l2 { compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; status = "okay"; }; reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; off-on-delay-us = <20000>; enable-active-high; }; reg_can_3v3: regulator-can-3v3 { compatible = "regulator-fixed"; regulator-name = "can-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "mx6ul-wm8960"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,widgets = "Microphone", "Mic Jack", "Line", "Line In", "Line", "Line Out", "Speaker", "Speaker", "Headphone", "Headphone Jack"; simple-audio-card,routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Speaker", "SPK_LP", "Speaker", "SPK_LN", "Speaker", "SPK_RP", "Speaker", "SPK_RN", "LINPUT1", "Mic Jack", "LINPUT3", "Mic Jack", "RINPUT1", "Mic Jack", "RINPUT2", "Mic Jack"; status = "disabled"; simple-audio-card,cpu { sound-dai = <&sai2>; status = "disabled"; }; dailink_master: simple-audio-card,codec { sound-dai = <&codec>; clocks = <&clks IMX6UL_CLK_SAI2>; status = "disabled"; }; }; sound-wm8960 { compatible = "fsl,imx6ul-evk-wm8960", "fsl,imx-audio-wm8960"; model = "wm8960-audio"; cpu-dai = <&sai2>; audio-codec = <&codec>; asrc-controller = <&asrc>; codec-master; gpr = <&gpr 4 0x100000 0x100000>; /* * hp-det = <hp-det-pin hp-det-polarity>; * hp-det-pin: JD1 JD2 or JD3 * hp-det-polarity = 0: hp detect high for headphone * hp-det-polarity = 1: hp detect high for speaker */ hp-det = <3 0>; hp-det-gpios = <&gpio5 4 0>; mic-det-gpios = <&gpio5 4 0>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", "Ext Spk", "SPK_RP", "Ext Spk", "SPK_RN", "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", "RINPUT1", "Main MIC", "RINPUT2", "Main MIC", "Mic Jack", "MICB", "Main MIC", "MICB", "CPU-Playback", "ASRC-Playback", "Playback", "CPU-Playback", "ASRC-Capture", "CPU-Capture", "CPU-Capture", "Capture"; }; spi4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; status = "okay"; pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; gpio-sck = <&gpio5 11 0>; gpio-mosi = <&gpio5 10 0>; cs-gpios = <&gpio5 7 0>; num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; gpio_spi: gpio@0 { compatible = "fairchild,74hc595"; gpio-controller; #gpio-cells = <2>; reg = <0>; registers-number = <1>; registers-default = /bits/ 8 <0x57>; spi-max-frequency = <100000>; }; }; }; &clks { assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <786432000>; }; &csi { status = "disabled"; port { csi1_ep: endpoint { remote-endpoint = <&ov5640_ep>; }; }; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; codec: wm8960@1a { #sound-dai-cells = <0>; compatible = "wlf,wm8960"; reg = <0x1a>; wlf,shared-lrclk; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; }; ov5640: ov5640@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi1>; clocks = <&clks IMX6UL_CLK_CSI>; clock-names = "csi_mclk"; pwn-gpios = <&gpio_spi 6 1>; rst-gpios = <&gpio_spi 5 0>; csi_id = <0>; mclk = <24000000>; mclk_source = <0>; status = "disabled"; port { ov5640_ep: endpoint { remote-endpoint = <&csi1_ep>; }; }; }; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; phy-mode = "rmii"; phy-handle = <ðphy0>; status = "okay"; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rmii"; phy-handle = <ðphy1>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@2 { reg = <2>; micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; }; ethphy1: ethernet-phy@1 { reg = <1>; micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET2_REF>; clock-names = "rmii-ref"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <®_can_3v3>; status = "okay"; }; &can2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <®_can_3v3>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; mag3110@e { compatible = "fsl,mag3110"; reg = <0x0e>; position = <2>; }; fxls8471@1e { compatible = "fsl,fxls8471"; reg = <0x1e>; position = <0>; interrupt-parent = <&gpio5>; interrupts = <0 8>; }; }; &lcdif { assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; display = <&display0>; status = "okay"; display0: display@0 { bits-per-pixel = <16>; bus-width = <24>; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <9200000>; hactive = <480>; vactive = <272>; hfront-porch = <8>; hback-porch = <4>; hsync-len = <41>; vback-porch = <2>; vfront-porch = <4>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; }; }; }; &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pxp { status = "okay"; }; &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; reg = <0>; }; }; &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, <&clks IMX6UL_CLK_SAI2>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <12288000>; fsl,sai-mclk-direction-output; status = "okay"; }; &snvs_poweroff { status = "okay"; }; &snvs_pwrkey { status = "okay"; }; &sim2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sim2>; assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; assigned-clock-rates = <240000000>; /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control * NCN8025:Vcc = ACTIVE_HIGH?5V:3V * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V */ pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; port = <1>; sven_low_active; status = "okay"; }; &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xfff>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; /* for DTE mode, add below change */ /* fsl,dte-mode; */ /* pinctrl-0 = <&pinctrl_uart2dte>; */ status = "okay"; }; &usbotg1 { dr_mode = "otg"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg1>; status = "okay"; }; &usbotg2 { dr_mode = "host"; disable-over-current; status = "okay"; }; &usbphy1 { fsl,tx-d-cal = <106>; }; &usbphy2 { fsl,tx-d-cal = <106>; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; keep-power-in-suspend; wakeup-source; vmmc-supply = <®_sd1_vmmc>; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; non-removable; keep-power-in-suspend; wakeup-source; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; }; &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 >; }; pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 >; }; pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 >; }; pinctrl_flexcan1: flexcan1grp{ fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 >; }; pinctrl_flexcan2: flexcan2grp{ fsl,pins = < MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 >; }; pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 >; }; pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 /* used for lcd reset */ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 >; }; pinctrl_qspi: qspigrp { fsl,pins = < MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; }; pinctrl_sai2: sai2grp { fsl,pins = < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 >; }; pinctrl_pwm1: pwm1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 >; }; pinctrl_sim2: sim2grp { fsl,pins = < MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 >; }; pinctrl_spi4: spi4grp { fsl,pins = < MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 >; }; pinctrl_tsc: tscgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 >; }; pinctrl_uart2dte: uart2dtegrp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 >; }; pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; }; pinctrl_usdhc2_8bit: usdhc2grp_8bit { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 >; }; pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 >; }; pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; };
imx6ull-14x14-evk.dts
// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (C) 2016 Freescale Semiconductor, Inc. /dts-v1/; #include "imx6ull.dtsi" #include "imx6ul-14x14-evk.dtsi" / { model = "Freescale i.MX6 ULL 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; }; &clks { assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>, <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <320000000>, <786432000>; }; &csi { status = "okay"; }; &ov5640 { status = "okay"; }; /delete-node/ &sim2;
imx6ul-14x14-evk-emmc.dts
/*
- Copyright 2019 NXP
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
*/
#include “imx6ul-14x14-evk.dts”
&usdhc2 {
pinctrl-names = “default”, “state_100mhz”, “state_200mhz”;
pinctrl-0 = <&pinctrl_usdhc2_8bit>;
pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
bus-width = <8>;
non-removable;
status = “okay”;
};
修改后
imx6ull-alientek.dtsi
// SPDX-License-Identifier: GPL-2.0 // // Copyright (C) 2015 Freescale Semiconductor, Inc. / { chosen { stdout-path = &uart1; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; linux,cma { compatible = "shared-dma-pool"; reusable; size = <0xa000000>; linux,cma-default; }; }; backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; status = "okay"; }; pxp_v4l2 { compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; status = "okay"; }; reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; //gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; off-on-delay-us = <20000>; enable-active-high; }; reg_can_3v3: regulator-can-3v3 { compatible = "regulator-fixed"; regulator-name = "can-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; //gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "mx6ul-wm8960"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,widgets = "Microphone", "Mic Jack", "Line", "Line In", "Line", "Line Out", "Speaker", "Speaker", "Headphone", "Headphone Jack"; simple-audio-card,routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Speaker", "SPK_LP", "Speaker", "SPK_LN", "Speaker", "SPK_RP", "Speaker", "SPK_RN", "LINPUT1", "Mic Jack", "LINPUT3", "Mic Jack", "RINPUT1", "Mic Jack", "RINPUT2", "Mic Jack"; status = "disabled"; simple-audio-card,cpu { sound-dai = <&sai2>; status = "disabled"; }; dailink_master: simple-audio-card,codec { sound-dai = <&codec>; clocks = <&clks IMX6UL_CLK_SAI2>; status = "disabled"; }; }; sound-wm8960 { compatible = "fsl,imx6ul-evk-wm8960", "fsl,imx-audio-wm8960"; model = "wm8960-audio"; cpu-dai = <&sai2>; audio-codec = <&codec>; asrc-controller = <&asrc>; codec-master; gpr = <&gpr 4 0x100000 0x100000>; /* * hp-det = <hp-det-pin hp-det-polarity>; * hp-det-pin: JD1 JD2 or JD3 * hp-det-polarity = 0: hp detect high for headphone * hp-det-polarity = 1: hp detect high for speaker */ hp-det = <3 0>; /* hp-det-gpios = <&gpio5 4 0>; mic-det-gpios = <&gpio5 4 0>; */ audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", "Ext Spk", "SPK_RP", "Ext Spk", "SPK_RN", "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", "RINPUT1", "Main MIC", "RINPUT2", "Main MIC", "Mic Jack", "MICB", "Main MIC", "MICB", "CPU-Playback", "ASRC-Playback", "Playback", "CPU-Playback", "ASRC-Capture", "CPU-Capture", "CPU-Capture", "Capture"; }; spi4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; status = "okay"; /* pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; */ gpio-sck = <&gpio5 11 0>; gpio-mosi = <&gpio5 10 0>; /* cs-gpios = <&gpio5 7 0>; */ num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; gpio_spi: gpio@0 { compatible = "fairchild,74hc595"; gpio-controller; #gpio-cells = <2>; reg = <0>; registers-number = <1>; registers-default = /bits/ 8 <0x57>; spi-max-frequency = <100000>; }; }; }; &clks { assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <786432000>; }; &csi { status = "disabled"; port { csi1_ep: endpoint { remote-endpoint = <&ov5640_ep>; }; }; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; codec: wm8960@1a { #sound-dai-cells = <0>; compatible = "wlf,wm8960"; reg = <0x1a>; wlf,shared-lrclk; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; }; ov5640: ov5640@3c { compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi1>; clocks = <&clks IMX6UL_CLK_CSI>; clock-names = "csi_mclk"; pwn-gpios = <&gpio_spi 6 1>; rst-gpios = <&gpio_spi 5 0>; csi_id = <0>; mclk = <24000000>; mclk_source = <0>; status = "disabled"; port { ov5640_ep: endpoint { remote-endpoint = <&csi1_ep>; }; }; }; /* paranoid FT5406/FT5426 */ ft5426: ft5426@38 { compatible = "edt,edt-ft5426","edt,edt-ft5406"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc &pinctrl_tsc_reset >; interrupt-parent = <&gpio1>; interrupts = <9 0>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; interrupt-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; status = "okay"; }; gt9147:gt9147@14 { compatible = "goodix,gt9147", "goodix,gt9xx"; reg = <0x14>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc &pinctrl_tsc_reset >; interrupt-parent = <&gpio1>; interrupts = <9 0>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; interrupt-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; status = "disable"; /* 如果需要改为okay */ }; /* paranoid sill902x,如果需要HDMI就将status改为okay即可 */ /* sii902x: sii902x@39 { compatible = "SiI,sii902x"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sii902x>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; mode_str = "1280x720M@60"; bits-per-pixel = <16>; resets = <&sii902x_reset>; reg = <0x39>; status = "disable"; };*/ }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_reset>; phy-mode = "rmii"; phy-handle = <ðphy0>; phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; phy-reset-duration = <200>; status = "okay"; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_reset>; phy-mode = "rmii"; phy-handle = <ðphy1>; phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; phy-reset-duration = <200>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; smsc,disable-energy-detect; reg = <0>; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; smsc,disable-energy-detect; reg = <1>; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <®_can_3v3>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; ap3216c@1e { compatible = "alientek,ap3216c"; reg = <0x1e>; }; ap3216c@1e { compatible = "alientek,ap3216c"; reg = <0x1e>; }; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; display = <&display0>; status = "okay"; /* 7寸1024*600 */ display0: display { bits-per-pixel = <24>; bus-width = <24>; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <51200000>; hactive = <1024>; vactive = <600>; hfront-porch = <160>; hback-porch = <140>; hsync-len = <20>; vback-porch = <20>; vfront-porch = <12>; vsync-len = <3>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; }; }; /* 4.3寸480*272 */ /* display0: display { bits-per-pixel = <24>; bus-width = <24>; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <9000000>; hactive = <480>; vactive = <272>; hfront-porch = <5>; hback-porch = <40>; hsync-len = <1>; vback-porch = <8>; vfront-porch = <8>; vsync-len = <1>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; }; };*/ /* 4.3寸800*480 */ /* display0: display { bits-per-pixel = <24>; bus-width = <24>; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <31000000>; hactive = <800>; vactive = <480>; hfront-porch = <40>; hback-porch = <88>; hsync-len = <48>; vback-porch = <32>; vfront-porch = <13>; vsync-len = <3>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; }; };*/ }; &ecspi3 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; /* cant't use cs-gpios! */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; spidev: icm20608@0 { compatible = "alientek,icm20608"; spi-max-frequency = <8000000>; reg = <0>; }; }; &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; clocks = <&clks IMX6UL_CLK_PWM3>, <&clks IMX6UL_CLK_PWM3>; status = "disable"; }; &adc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; num-channels = <2>; vref-supply = <®_can_3v3>; status = "okay"; }; &pxp { status = "okay"; }; &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; reg = <0>; }; }; &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, <&clks IMX6UL_CLK_SAI2>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <0>, <12288000>; fsl,sai-mclk-direction-output; status = "okay"; }; &snvs_poweroff { status = "okay"; }; &snvs_pwrkey { status = "okay"; }; &sim2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sim2>; assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; assigned-clock-rates = <240000000>; /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control * NCN8025:Vcc = ACTIVE_HIGH?5V:3V * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V */ pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; port = <1>; sven_low_active; status = "okay"; }; &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; /* xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;*/ measure-delay-time = <0xffff>; pre-charge-time = <0xfff>; status = "disable"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; &usbotg1 { dr_mode = "otg"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg1>; status = "okay"; }; &usbotg2 { dr_mode = "host"; disable-over-current; status = "okay"; }; &usbphy1 { fsl,tx-d-cal = <106>; }; &usbphy2 { fsl,tx-d-cal = <106>; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; keep-power-in-suspend; wakeup-source; vmmc-supply = <®_sd1_vmmc>; status = "okay"; no-1-8-v; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; non-removable; keep-power-in-suspend; wakeup-source; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; }; &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 >; }; /* paranoid ECSPI */ pinctrl_ecspi3: icm20608 { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* CS */ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b1 /* SCLK */ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b1 /* MISO */ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b1 /* MOSI */ >; }; /* paranoid ADC1_CH1 GPIO1_IO01 */ pinctrl_adc1: adc1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 >; }; /* paranoid HDMI RGB */ pinctrl_hdmi_dat: hdmidatgrp { /* do not change the pimux vlaue on alpaha and mini board*/ fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x49 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x49 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x49 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x49 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x49 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x49 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x49 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x49 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x49 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x49 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x49 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x49 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x49 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x49 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x49 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x51 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x49 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x49 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x49 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x49 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x49 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x49 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x49 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x49 >; }; /* paranoid HDMI RGB */ pinctrl_hdmi_ctrl: hdmictrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x49 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x49 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x49 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x49 >; }; pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 >; }; pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x10b0 >; }; pinctrl_flexcan1: flexcan1grp{ fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 >; }; pinctrl_flexcan2: flexcan2grp{ fsl,pins = < /* MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 */ >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 >; }; pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x49 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x49 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x49 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x49 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x49 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x49 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x49 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x49 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x49 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x49 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x49 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x49 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x49 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x49 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x49 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x49 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x49 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x49 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x49 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x49 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x49 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x49 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x49 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x49 >; }; pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x49 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x49 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x7949 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x49 /* used for lcd reset */ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49 >; }; /* paranoid SII902X INT*/ pinctrl_sii902x: hdmigrp-1 { fsl,pins = < /*MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11*/ >; }; /* paranoid PWM3 GPIO1_IO04 */ pinctrl_pwm3: pwm3grp { fsl,pins = < MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x110b0 >; }; /* paranoid ADC1_CH1 GPIO1_IO01 */ pinctrl_adc1: adc1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 >; }; pinctrl_qspi: qspigrp { fsl,pins = < MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; }; pinctrl_sai2: sai2grp { fsl,pins = < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 >; }; pinctrl_pwm1: pwm1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 >; }; pinctrl_sim2: sim2grp { fsl,pins = < MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 >; }; pinctrl_spi4: spi4grp { fsl,pins = < MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 /* MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 */ >; }; pinctrl_tsc: tscgrp { fsl,pins = < /* 7寸RGB屏幕，FT5426 */ /* MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0xF080 */ /* TSC_INT */ /* 7寸RGB屏幕,GT9147 */ /* MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x10B0 */ /* TSC_INT */ >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < /* MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 */ MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 >; }; pinctrl_uart2dte: uart2dtegrp { fsl,pins = < /* MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 */ >; }; /* paranoid */ pinctrl_uart3: uart3grp { fsl,pins = < MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0X1b0b1 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0X1b0b1 >; }; pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f1 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f1 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f1 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; }; pinctrl_usdhc2_8bit: usdhc2grp_8bit { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 >; }; pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 >; }; pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; }; &iomuxc_snvs { pinctrl-names = "default_snvs"; pinctrl-0 = <&pinctrl_hog_2>; imx6ul-evk { /* zuozhongkai Touch RESET */ pinctrl_tsc_reset: tsc_reset { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x10B0 >; }; /* zuozhongkai RGB RESET */ ts_reset_hdmi_pin: ts_reset_hdmi_mux { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x49 >; }; pinctrl_hog_2: hoggrp-2 { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 >; }; pinctrl_dvfs: dvfsgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 >; }; pinctrl_lcdif_reset: lcdifresetgrp { fsl,pins = < /* used for lcd reset */ /* MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 */ >; }; pinctrl_sai2_hp_det_b: sai2_hp_det_grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 >; }; /*enet1 reset zuozhongkai*/ pinctrl_enet1_reset: enet1resetgrp { fsl,pins = < /* used for enet1 reset */ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */ >; }; /*enet2 reset zuozhongkai*/ pinctrl_enet2_reset: enet2resetgrp { fsl,pins = < /* used for enet2 reset */ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x10B0 /* ENET2 RESET */ >; }; }; };
imx6ull-alientek.dts
// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (C) 2016 Freescale Semiconductor, Inc. /dts-v1/; #include "imx6ull.dtsi" #include "imx6ull-alientek.dtsi" / { model = "Freescale i.MX6 ULL 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; }; &clks { assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>, <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; assigned-clock-rates = <320000000>, <786432000>; }; &csi { status = "okay"; }; &ov5640 { status = "okay"; }; /delete-node/ &sim2;
imx6ull-alientek-emmc.dts
/*
- Copyright 2019 NXP
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
*/
#include “imx6ull-alientek.dts”
&usdhc2 {
pinctrl-names = “default”, “state_100mhz”, “state_200mhz”;
pinctrl-0 = <&pinctrl_usdhc2_8bit>;
pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
bus-width = <8>;
non-removable;
status = “okay”;
};
2 修改网络驱动代码
Linux 驱动开发的时候要用到网络调试驱动，所以必须要把网络驱动调试好。在讲解 uboot 移植的时候就已经说过了，正点原子开发板的网络和 NXP 官方的网络硬件上不同，网络 PHY 芯片由 KSZ8081 换为了 LAN8720A，两个网络 PHY 芯片的复位 IO 也不同。所以 Linux 内核自带的网络驱动是驱动不起来 I.MX6U-ALPHA 开发板上的网络的，需要做修改。
1、修改 fec_main.c 文件
要 在 I.MX6ULL 上 使 用 LAN8720A ， 需 要 修 改 一 下 Linux 内 核 源 码 ， 打 开drivers/net/ethernet/freescale/fec_main.c，找到函数 fec_probe，在 fec_probe 中加入如下代码：
修改前
3438 static int 3439 fec_probe(struct platform_device *pdev) 3440 { 3441 struct fec_enet_private *fep; 3442 struct fec_platform_data *pdata; 3443 struct net_device *ndev; 3444 int i, irq, ret = 0; 3445 struct resource *r; 3446 const struct of_device_id *of_id; 3447 static int dev_id; 3448 struct device_node *np = pdev->dev.of_node, *phy_node; 3449 int num_tx_qs; 3450 int num_rx_qs; 3451 3452 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3453 3454 /* Init network device */ 3455 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3456 num_tx_qs, num_rx_qs); 3457 if (!ndev) 3458 return -ENOMEM; 3459 3460 SET_NETDEV_DEV(ndev, &pdev->dev); 3461 3462 /* setup board info structure */ 3463 fep = netdev_priv(ndev); 3464 3465 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3466 if (of_id) 3467 pdev->id_entry = of_id->data; 3468 fep->quirks = pdev->id_entry->driver_data; 3469 3470 fep->netdev = ndev; 3471 fep->num_rx_queues = num_rx_qs; 。。。。。
修改后
static int 3439 fec_probe(struct platform_device *pdev) 3440 { 3441 struct fec_enet_private *fep; 3442 struct fec_platform_data *pdata; 3443 struct net_device *ndev; 3444 int i, irq, ret = 0; 3445 struct resource *r; 3446 const struct of_device_id *of_id; 3447 static int dev_id; 3448 struct device_node *np = pdev->dev.of_node, *phy_node; 3449 int num_tx_qs; 3450 int num_rx_qs; 3451 3452 /* 设置 MX6UL_PAD_ENET1_TX_CLK 和 MX6UL_PAD_ENET2_TX_CLK 3453 * 这两个 IO 的复用寄存器的 SION 位为 1。 3454 */ 3455 void __iomem *IMX6U_ENET1_TX_CLK; 3456 void __iomem *IMX6U_ENET2_TX_CLK; 3457 3458 IMX6U_ENET1_TX_CLK = ioremap(0X020E00DC, 4); 3459 writel(0X14, IMX6U_ENET1_TX_CLK); 3460 3461 IMX6U_ENET2_TX_CLK = ioremap(0X020E00FC, 4); 3462 writel(0X14, IMX6U_ENET2_TX_CLK); 3463 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3464 3465 /* Init network device */ 3466 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), 3467 num_tx_qs, num_rx_qs); 3468 if (!ndev) 3469 return -ENOMEM; 3470 3471 SET_NETDEV_DEV(ndev, &pdev->dev); 3472 3473 /* setup board info structure */
第 3455~3462 就是新加入的代码，如果要在 I.MX6ULL 上使用 LAN8720A 就需要设置ENET1 和 ENET2 的 TX_CLK 引脚复位寄存器的 SION 位为 1。
2、修改 smsc.c 文件
首先需要找到 LAN8720A 的驱动文件， LAN8720A 的驱动文件是 drivers/net/phy/smsc.c，在此文件中有个叫做 smsc_phy_reset 的函数，看名字都知道这是 SMSC PHY 的复位函数，因此， LAN8720A 肯定也会使用到这个复位函数， 修改此函数的内容，修改以后的 smsc_phy_reset函数内容如下所示：
修改前
60 static int smsc_phy_reset(struct phy_device *phydev) 61 { 62 int rc = phy_read(phydev, MII_LAN83C185_SPECIAL_MODES); 63 if (rc < 0) 64 return rc; 65 66 /* If the SMSC PHY is in power down mode, then set it 67 * in all capable mode before using it. 68 */ 69 if ((rc & MII_LAN83C185_MODE_MASK) == MII_LAN83C185_MODE_POWERDOWN) { 70 int timeout = 50000; 71 72 /* set "all capable" mode and reset the phy */ 73 rc |= MII_LAN83C185_MODE_ALL; 74 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc); 75 phy_write(phydev, MII_BMCR, BMCR_RESET); 76 77 /* wait end of reset (max 500 ms) */ 78 do { 79 udelay(10); 80 if (timeout-- == 0) 81 return -1; 82 rc = phy_read(phydev, MII_BMCR); 83 } while (rc & BMCR_RESET); 84 } 85 return 0; 86 }
修改后
static int smsc_phy_reset(struct phy_device *phydev) { int err, phy_reset; int msec = 1; struct device_node *np; int timeout = 50000; if(phydev->addr == 0) /* FEC1 */ { np = of_find_node_by_path("/soc/aips-bus@02100000/ethernet@02188000"); if(np == NULL) { return -EINVAL; } } if(phydev->addr == 1) /* FEC2 */ { np = of_find_node_by_path("/soc/aips-bus@02000000/ethernet@020b4000"); if(np == NULL) { return -EINVAL; } } err = of_property_read_u32(np, "phy-reset-duration", &msec); /* A sane reset duration should not be longer than 1s */ if (!err && msec > 1000) msec = 1; phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); if (!gpio_is_valid(phy_reset)) return; gpio_direction_output(phy_reset, 0); gpio_set_value(phy_reset, 0); msleep(msec); gpio_set_value(phy_reset, 1); int rc = phy_read(phydev, MII_LAN83C185_SPECIAL_MODES); if (rc < 0) return rc; /* If the SMSC PHY is in power down mode, then set it * in all capable mode before using it. */ 102 if ((rc & MII_LAN83C185_MODE_MASK) == MII_LAN83C185_MODE_POWERDOWN) { 103 104 /* set "all capable" mode and reset the phy */ 105 rc |= MII_LAN83C185_MODE_ALL; 106 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc); 107 } 108 phy_write(phydev, MII_BMCR, BMCR_RESET); 109 110 /* wait end of reset (max 500 ms) */ 111 do { 112 udelay(10); 113 if (timeout-- == 0) 114 return -1; 115 rc = phy_read(phydev, MII_BMCR); 116 } while (rc & BMCR_RESET); 117 118 return 0; 119 }
第 7~12 行，获取 FEC1 网卡对应的设备节点。
第 14~19 行，获取 FEC2 网卡对应的设备节点。
第 21 行，从设备树中获取“phy-reset-duration”属性信息，也就是复位时间。
第 25 行，从设备树中获取“phy-reset-gpios”属性信息，也就是复位 IO。
第 29~32 行，设置 PHY 的复位 IO，复位 LAN8720A。
第 41~48 行，以前的 smsc_phy_reset 函数会判断 LAN8720 是否处于 Powerdown 模式，只有处于 Powerdown 模式的时候才会软复位 LAN8720。这里我们将软复位代码移出来，这样每次调用 smsc_phy_reset 函数 LAN8720A 都会被软复位。最后我们还需要在 drivers/net/phy/smsc.c 文件中添加两个头文件，因为修改后的smsc_phy_reset 函数用到了 gpio_direction_output 和 gpio_set_value 这两个函数，需要添加的头文件如下所示：
#include <linux/of_gpio.h> #include <linux/io.h>
然后编译源码，启动开发板
4.结果
1.成功进入内核
2.网络检查
3.版本信息
