1单选(2分)
设计一个需要16个状态的控制器电路，使用哪种编码方式需要的触发器最多？尽管使用的触发器最多，但是这种编码方式使得在状态比较时仅仅需要比较一个位，可能节省译码逻辑需要的片上资源。
得分/总分
A.二进制编码Sequential
B.独热编码one-hot
C.格雷码Gray
D.约翰逊码Johnson
正确答案：B
2单选(2分)
下面哪一种是one-hot编码
得分/总分
A.0：0000
1：0001
2：0011
3：0111
B.0：0001
1：0010
2：0100
3：1000
C.0：0000
1：0001
2：0011
3：0010
D.0：0000
1：0001
2：0010
3：0011
正确答案：B你选对了
3多选(3分)
有限状态机的应用包括
得分/总分
A.网络协议
B.软件应用
C.硬件电路控制器系统
D.编译器
正确答案：A、B、C、D
4多选(3分)
状态机的编码方式可以是（）
得分/总分
A.格雷码Gray
B.约翰逊码Johnson
C.二进制编码Sequential
D.独热编码one-hot
正确答案：A、B、C、D
5多选(3分)
哪种编码方式在相邻状态转换时只有一个状态位发生翻转
得分/总分
A.格雷码Gray
B.二进制编码Sequential
C.约翰逊码Johnson
D.独热编码one-hot
正确答案：A、C
6多选(3分)
选出摩尔型状态机
得分/总分
A.
(input clk,acc,brake,reset, output [1:0] speed ); reg [1:0] state; localparam STOP=2'b00; localparam LOW=2'b01; localparam MEDIUM=2'b10; localparam HIGH =2'b11; assign speed=state; always@(posedge clk) case(state) STOP: if (acc && !brake) state=LOW; LOW: if (brake)state=STOP; else if (acc) state=MEDIUM; MEDIUM: if (brake)state=LOW; else if (acc)state=HIGH; HIGH: if (brake) state=MEDIUM; elsestate=HIGH; endcase endmodule
B.
module fsm (input clk,acc,brake,reset, input easy, output [1:0] speed ); reg [1:0] state; reg [1:0] next_state; localparam STOP=2'b00; localparam LOW=2'b01; localparam MEDIUM=2'b10; localparam HIGH =2'b11; //状态转换 always@(posedge clk or posedeg reset) if(reset) state=STOP; elsestate=next_state; //次态计算 always@(*) case(state) STOP: if (acc && !brake) next_state=LOW; else next_state=STOP; LOW: if (brake) next_state=STOP; else if (acc) next_state=MEDIUM; else next_state=LOW; MEDIUM: if (brake) next_state=LOW; else if (acc) next_state=HIGH; else next_state=MEDIUM; HIGH: if (brake) next_state=MEDIUM; else next_state=HIGH; endcase //输出逻辑 assign speed=easy ? 2'b01:state; endmodule
C.
module fsm (input clk,acc,brake,reset, output [1:0] speed ); enum bit [3:0] { STOP=4'b0001, LOW =4'b0010, MEDIUM=4'b0100, HIGH=4'b1000, }state,next_state; always@(posedge clk or posedeg reset) if(reset) state=STOP; elsestate=next_state; always@(*) case(state) STOP: speed=2'b00; if (acc && !brake) next_state=LOW; else next_state=STOP; LOW: speed=2'b01; if (brake) next_state=STOP; else if (acc) next_state=MEDIUM; else next_state=LOW; MEDIUM: speed=2'b10; if (brake) next_state=LOW; else if (acc) next_state=HIGH; else next_state=MEDIUM; HIGH: speed=2'b110; if (brake) next_state=MEDIUM; else next_state=HIGH; endcase endmodule
D.
module fsm (input clk,acc,brake,reset, output [1:0] speed ); reg [1:0] state; reg [1:0] next_state; localparam STOP=2'b00; localparam LOW=2'b01; localparam MEDIUM=2'b10; localparam HIGH =2'b11; //状态转换 always@(posedge clk or posedeg reset) if(reset) state=STOP; elsestate=next_state; //次态计算 always@(*) case(state) STOP: if (acc && !brake) next_state=LOW; else next_state=STOP; LOW: if (brake) next_state=STOP; else if (acc) next_state=MEDIUM; else next_state=LOW; MEDIUM: if (brake) next_state=LOW; else if (acc) next_state=HIGH; else next_state=MEDIUM; HIGH: if (brake) next_state=MEDIUM; else next_state=HIGH; endcase //输出逻辑 assign speed=state; endmodule
正确答案：A、C、D
7多选(3分)
设计FSM应该注意（）
得分/总分
A.复位后状态机应该有一个确定的状态
B.建议使用参数定义状态编码，状态名称尽量反映其含义
C.建议先画状态图再写代码
D.建议采用三段式结构
正确答案：A、B、C、D
8判断(2分)
有限状态机Finite State Machine是表示有限个状态以及在这些状态之间的转移和动作等行为的数学模型，状态机应用范围很广，例如硬件电路系统设计。
得分/总分
A.×
B.√
正确答案：B
9判断(2分)
在数字电路中，可以使用逻辑逻辑门和触发器构建状态机。更具体地说，状态机是组合逻辑和时序逻辑的特殊组合，硬件实现上需要一个用来存储状态的寄存器（时序逻辑块），一个决定状态转换的组合逻辑块，以及一个决定状态机输出的组合逻辑块。
得分/总分
A.√
B.×
正确答案：A
10判断(2分)
摩尔Moore型状态机的输出仅取决于当前状态，即当输入信号有变化时，输出在整个状态期间保持不变
得分/总分
A.√
B.×
正确答案：A
11判断(2分)
米利Mealy型状态机的输出除了受当前状态影响，还直接受输入影响，因此输出变化可能出现在任何时刻
得分/总分
A.√
B.×
正确答案：A
12判断(2分)
以下是一个米利型状机
module fsm (input clk,acc,brake,reset, output [1:0] speed ); reg [1:0] state; reg [1:0] next_state; localparam STOP=2'b00; localparam LOW=2'b01; localparam MEDIUM=2'b10; localparam HIGH =2'b11; //状态转换 always@(posedge clk or posedeg reset) if(reset) state=STOP; elsestate=next_state; //次态计算 always@(*) case(state) STOP: if (acc && !brake) next_state=LOW; else next_state=STOP; LOW: if (brake) next_state=STOP; else if (acc) next_state=MEDIUM; else next_state=LOW; MEDIUM: if (brake) next_state=LOW; else if (acc) next_state=HIGH; else next_state=MEDIUM; HIGH: if (brake) next_state=MEDIUM; else next_state=HIGH; endcase //输出逻辑 assign speed=state; endmodule
A.√
B.×
正确答案：B你选对了
解析：输出只有当前状态有关，3段式结构描述，是摩尔型状态机
13判断(2分)
SystemVerilog里可以使用枚举类型定义状态编码，关键字enum.
得分/总分
A.√
B.×
正确答案：A你选对了
14判断(2分)
参数化设计方法中，parameter和localparam定义的参数，在顶层模块中实例化时都可以传递到底层模块。
得分/总分
A.√
B.×
正确答案：B你选对了
解析：localparam的作用域仅仅限于当前module，不能作为参数传递的接口。
15判断(2分)
以下是一个摩尔型状态机
module fsm (input clk,acc,brake,reset, input easy, output [1:0] speed ); reg [1:0] state; reg [1:0] next_state; localparam STOP=2'b00; localparam LOW=2'b01; localparam MEDIUM=2'b10; localparam HIGH =2'b11; //状态转换 always@(posedge clk or posedeg reset) if(reset) state=STOP; elsestate=next_state; //次态计算 always@(*) case(state) STOP: if (acc && !brake) next_state=LOW; else next_state=STOP; LOW: if (brake) next_state=STOP; else if (acc) next_state=MEDIUM; else next_state=LOW; MEDIUM: if (brake) next_state=LOW; else if (acc) next_state=HIGH; else next_state=MEDIUM; HIGH: if (brake) next_state=MEDIUM; else next_state=HIGH; endcase //输出逻辑 assign speed=easy ? 2'b01:state; endmodule
得分/总分
A.√
B.×
正确答案：B你选对了
解析：输出不仅和当前状态有关，输入的变化可能随时改变输出，3段式结构描述，是米利型状态机
实验代码
无标准答案，请自由发挥
`default_nettype none module VirtualBoard ( input wire CLOCK, // 10 MHz Input Clock input wire [19:0] PB, // 20 Push Buttons, logical 1 when pressed input wire [35:0] S, // 36 Switches output wire [35:0] L, // 36 LEDs, drive logical 1 to light up output wire [7:0] SD7, // 8 common anode Seven-segment Display output wire [7:0] SD6, output wire [7:0] SD5, output wire [7:0] SD4, output wire [7:0] SD3, output wire [7:0] SD2, output wire [7:0] SD1, output wire [7:0] SD0 ); /** The input port is replaced with an internal signal **/ wire reset = PB[0]; wire clk; // = PB[1]; wire direction = S[0]; /************* The logic of this experiment *************/ /* 对10MHz系统时钟进行分频，使用分频后的时钟作为移位寄存器的时钟。 分频系数为10M，输出的clkout的频率为1Hz。 */ ClockDivider #(.RATIO(10000000)) divider_inst(.ClkIn(CLOCK), .Reset(reset), .ClkOut(clk)); // Finite State Machine wire [12:0] pattern; enum bit [3:0] { STATE0 = 4'b0000, STATE1 = 4'b0001, STATE2 = 4'b0010, STATE3 = 4'b0011, STATE4 = 4'b0100, STATE5 = 4'b0101, STATE6 = 4'b0110, STATE7 = 4'b0111, STATE8 = 4'b1000, STATE9 = 4'b1001 } state, next_state; always_ff @(posedge clk, posedge reset) begin if (reset) state <= STATE0; else state <= next_state; end always_comb begin : set_next_state case (state) STATE0: begin if (direction==0) next_state = STATE1; else next_state = STATE9; end STATE1: begin if (direction==0) next_state = STATE2; else next_state = STATE0; end STATE2: begin if (direction==0) next_state = STATE3; else next_state = STATE1; end STATE3: begin if (direction==0) next_state = STATE4; else next_state = STATE2; end STATE4: begin if (direction==0) next_state = STATE5; else next_state = STATE3; end STATE5: begin if (direction==0) next_state = STATE6; else next_state = STATE4; end STATE6: begin if (direction==0) next_state = STATE7; else next_state = STATE5; end STATE7: begin if (direction==0) next_state = STATE8; else next_state = STATE6; end STATE8: begin if (direction==0) next_state = STATE9; else next_state = STATE7; end STATE9: begin if (direction==0) next_state = STATE0; else next_state = STATE8; end endcase end : set_next_state always_comb begin : set_outputs case (state) STATE0: begin pattern = 13'b1111110111111; end STATE1: begin pattern = 13'b1001010010100; end STATE2: begin pattern = 13'b1110111110111; end STATE3: begin pattern = 13'b1111011110111; end STATE4: begin pattern = 13'b1001011111101; end STATE5: begin pattern = 13'b1111011101111; end STATE6: begin pattern = 13'b1111111101111; end STATE7: begin pattern = 13'b1001010010111; end STATE8: begin pattern = 13'b1111111111111; end STATE9: begin pattern = 13'b1111011111111; end endcase end : set_outputs /****** Internal signal assignment to output port *******/ assign L[12:0] = pattern; endmodule
