module addergen1 (co, sum, a, b, ci);
parameter SIZE = 4;
output [SIZE-1:0] sum;
output co;
input [SIZE-1:0] a, b;
input ci;
wire [SIZE :0] c;
genvar i;
assign c[0] = ci;
// Hierarchical gate instance names are:
// xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1
// bit[0].g2 bit[1].g2 bit[2].g2 bit[3].g2
// and gates: bit[0].g3 bit[1].g3 bit[2].g3 bit[3].g3
// bit[0].g4 bit[1].g4 bit[2].g4 bit[3].g4
// or gates: bit[0].g5 bit[1].g5 bit[2].g5 bit[3].g5
// Gate instances are connected with nets named:
// bit[0].t1 bit[1].t1 bit[2].t1 bit[3].t1
// bit[0].t2 bit[1].t2 bit[2].t2 bit[3].t2
// bit[0].t3 bit[1].t3 bit[2].t3 bit[3].t3
for(i=0; i<SIZE; i=i+1)  
begin:bit
wire t1, t2, t3;
xor g1 ( t1, a[i], b[i]);
xor g2 ( sum[i], t1, c[i]);
and g3 ( t2, a[i], b[i]);
and g4 ( t3, t1, c[i]);
or g5 ( c[i+1], t2, t3);
end
assign co = c[SIZE];
endmodule

loop_generate_construct ::=
     for ( genvar_initialization ; genvar_expression ; genvar_iteration )
     generate_block

module
multiplier(a,b,product);
parameter a_width = 8, b_width = 8;
localparam product_width = a_width+b_width;
// cannot be modified directly with the defparam
// statement or the module instance statement #
input [a_width-1:0] a;
input [b_width-1:0] b;
output [product_width-1:0] product;
generate
if((a_width < 8) || (b_width < 8))
begin:mult
CLA_multiplier #(a_width,b_width) u1(a, b, product);
// instantiate a CLA multiplier
end
else begin:mult
WALLACE_multiplier #(a_width,b_width) u1(a, b, product);
// instantiate a Wallace-treemultiplier
end
endgenerate
// The hierarchical instance name is mult.u1
endmodule

generate
case (WIDTH)
1: begin: adder // 1-bit adder implementation
adder_1bit x1(co, sum, a, b, ci);
end
2: begin: adder // 2-bit adder implementation
adder_2bit x1(co, sum, a, b, ci);
end
default:
begin: adder // others - carry look-ahead adder
adder_cla #(WIDTH) x1(co, sum, a, b, ci);
end
endcase
// The hierarchical instance name is adder.x1
endgenerate

module mod_a;
genvar i;
//"generate","endgenerate" keywords are not required
for begin:a
(i=0; i<5; i=i+1)
for begin:b
(i=0; i<5; i=i+1)
...
// error -- using "i" as loop index for
...
// two nested generate loops
end
end

module mod_b;
genvar i;
reg a;
for (i=1; i<0; i=i+1) begin: a
... // error -- "a" conflicts with name of reg "a"
end
endmodule