Verilog代码的风格规范

module mux4_to_1(out, in0, in1, in2, in3, s1, s0);
    input [1:0] in0, in1, in2, in3;
    input s1, s0;
    output reg [1:0] out;
//变量声明后空行
always @(*)
begin
    case ({s1,s0})
        2'b00: out = in0;
        2'b01: out = in1;
        2'b10: out = in2;
        default: out = in3;
    endcase
end
endmodule
//两模块间空行
module mux2_to_1(/*...*/);
    /**/
endmodule

module mux4_to_1(out, in0, in1, in2, in3, s1, s0); //模块名后不留空格
    input [1:0] in0, in1, in2, in3;
    input s1, s0;
    output reg [1:0] out;
    always @(*) //关键字后空格（always后加空格）
    begin
        //关键字后空格（case后加空格）
        case ({s1, s0})
            2'b00: out = in0; //分号向前紧跟
            2'b01: out = in1;
            //赋值运算符、关系运算符、算术运算符、逻辑运算符、位运算符等双目运算符前后都要加空格
            2'b10: out = in2;
            default: out = in3;
        endcase
    end
endmodule
//单目运算符前后不加空格

module mux4_to_1(out, in0, in1, in2, in3, s1, s0);
    input [1:0] in0, in1, in2, in3;
    input s1, s0;
    output reg [1:0] out;
    always @(*)
    begin
      case ({s1,s0}) //case在always里，要缩进
        2'b00: out = in0; //case的的每一条在case里，也要缩进
        2'b01: out = in1;
        2'b10: out = in2;
        default: out = in3;
    endcase
end
endmodule

module mux4_to_1(out, in0, in1, in2, in3, s1, s0);
    input [1:0] in0, in1, in2, in3;
    input s1, s0;
    output reg [1:0] out;
    always @(*)
    begin //begin和end要独占一行，且不缩进
    case ({s1,s0})
        2'b00: out = in0;
        2'b01: out = in1;
        2'b10: out = in2;
        default: out = in3;
    endcase
end
endmodule

module mux4_to_1(out, in0, in1, in2, in3, s1, s0);
    input [1:0] in0, in1, in2, in3;
    input s1, s0;
    output reg [1:0] out;
    always @(*) //always、if、else等独占一行
    begin
        case ({s1,s0})
            2'b00: out = in0; //一行代码只做一件事情，如只写一条语句
            2'b01: out = in1;
            2'b10: out = in2;
            default: out = in3;
        endcase
    end
endmodule

module mux4_to_1(out, in0, in1, in2, in3, s1, s0); //注释开始符号与代码之间有空格
    input [1:0] in0, in1, in2, in3;//4个待选输入
    input s1, s0; //选择信号
    output reg [1:0] out; //存放被选择出的数据
    always @(*)
    begin
        case ({s1,s0})
            2'b00: out = in0; //in0的值赋给out <- 这是一条多余注释
            2'b01: out = in1;
            2'b10: out = in2;
            default: out = in3;
        endcase
    end
endmodule