这里的话我用的是vivado的开发工具
配置shift ram可以实现两行数据的移位，
那再串上一行就可以实现说行数据的移位功能
配置下图：
其他的默认就行，这里我因为是对200*200 *8bit图片数据的进行处理，所以就主要把 位宽和深度定义为自己想要的就好了
moduleShift_RAM_3X3( //globalsignalsinputclk, inputrst_n, //Imagedataprepredtobeprocessdinputper_clken,//PreparedImagedataoutput/captureenableclockinput [7:0] per_img_Y,//PreparedImagebrightnessinput//Imagedatahasbeenprocessdoutputmatrix_clken, //PreparedImagedataoutput/captureenableclockoutputreg [7:0] matrix_p11, outputreg [7:0] matrix_p12, outputreg [7:0] matrix_p13, //3X3Matrixoutputoutputreg [7:0] matrix_p21, outputreg [7:0] matrix_p22, outputreg [7:0] matrix_p23, outputreg [7:0] matrix_p31, outputreg [7:0] matrix_p32, outputreg [7:0] matrix_p33 ); //----------------------------------------------//consume1clkwire [7:0] row1_data;//framedataofthe1throwwire [7:0] row2_data;//framedataofthe2throwreg [7:0] row3_data;//framedataofthe3throwalways@(posedgeclkornegedgerst_n)beginif(!rst_n) row3_data<=8'b0;elsebeginif(per_clken) row3_data<=per_img_Y; elserow3_data<=row3_data; endend//----------------------------------------------------------//moduleofshiftramforrowdatawireshift_clk_en=per_clken; //Shift_RAM_3X3_8bit1Shift_RAM_3X3_8bitu1_Shift_RAM_3X3_8bit ( .D(row3_data), //inputwire [7 : 0] D .CLK(shift_clk_en), //inputwireCLK .SCLR(~rst_n), //inputwireSCLR .Q(row2_data) //outputwire [7 : 0] Q); //Shift_RAM_3X3_8bit2Shift_RAM_3X3_8bitu2_Shift_RAM_3X3_8bit ( .D(row2_data), //inputwire [7 : 0] D .CLK(shift_clk_en), //inputwireCLK .SCLR(~rst_n), //inputwireSCLR .Q(row1_data) //outputwire [7 : 0] Q); //-------------------------------------------//per_clkendelay3clkreg [1:0] per_clken_r; always@(posedgeclkornegedgerst_n)beginif(!rst_n) per_clken_r<=2'b0;elseper_clken_r<= {per_clken_r[0], per_clken}; endwireread_clken=per_clken_r[0]; assignmatrix_clken=per_clken_r[1]; //---------------------------------------------------------------------/****************************************(1)readdatafromshift_RAM(2)caulatethesobel(3)steadydataaftersobelgenerate******************************************///wire [23:0] matrix_row1= {matrix_p11, matrix_p12,matrix_p13};//justfortest//wire [23:0] matrix_row2= {matrix_p21, matrix_p22,matrix_p23}; //wire [23:0] matrix_row3= {matrix_p31, matrix_p32,matrix_p33}; always@(posedgeclkornegedgerst_n)beginif(!rst_n)begin {matrix_p11, matrix_p12, matrix_p13} <=24'h0; {matrix_p21, matrix_p22, matrix_p23} <=24'h0; {matrix_p31, matrix_p32, matrix_p33} <=24'h0;end//elseif(read_frame_href)beginelseif(read_clken)begin//shift_RAMdatareadclockenbale {matrix_p11, matrix_p12, matrix_p13} <= {matrix_p12, matrix_p13, row1_data};//1thshiftinput {matrix_p21, matrix_p22, matrix_p23} <= {matrix_p22, matrix_p23, row2_data};//2thshiftinput {matrix_p31, matrix_p32, matrix_p33} <= {matrix_p32, matrix_p33, row3_data};//3thshiftinputendelsebegin {matrix_p11, matrix_p12, matrix_p13} <= {matrix_p11, matrix_p12, matrix_p13}; {matrix_p21, matrix_p22, matrix_p23} <= {matrix_p21, matrix_p22, matrix_p23}; {matrix_p31, matrix_p32, matrix_p33} <= {matrix_p31, matrix_p32, matrix_p33}; end//end/*elsebegin {matrix_p11, matrix_p12, matrix_p13} <=24'h0; {matrix_p21, matrix_p22, matrix_p23} <=24'h0; {matrix_p31, matrix_p32, matrix_p33} <=24'h0;end*/endendmodule
