我做了个利用rom进行同步fifo的读写并把读出的数据输出到ram里并读出数据检验数据的正确性
直接贴代码吧，没什么难度：都是IP核的应用熟悉下流程
`timescale1ns/1psmodulerom_fifo_controller(clk,rst_n,fifo_full,fifo_empty,ram_rddb ); inputclk; inputrst_n; //--------------------------------------------------outputfifo_full; outputfifo_empty; output [7:0]ram_rddb; //--------------------------------------------------wire [7:0]rom_out; wire [7:0]fifo_rddb; //--------------------------------------------------reg [8:0]cnt; always@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)begincnt<=1'b0;endelsebegincnt<=cnt+1; endendromuut_rom( .clka(clk), //inputclka .addra(cnt), //input [3 : 0] addra .douta(rom_out) //output [7 : 0] douta); regwr_en; reg [7:0]wr_data; always@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)beginwr_en<=1'b0;wr_data<=1'b0;endelseif(cnt>9'd0&&cnt<9'd11)beginwr_en<=1'b1;wr_data<=rom_out; endelsebeginwr_en<=1'b0;wr_data<=1'b0;endendregrd_en; always@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)beginrd_en<=1'b0;endelseif(cnt>9'd20&&cnt<9'd31)beginrd_en<=1'b1;endelsebeginrd_en<=1'b0;endendregrd_rdrdy; always@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)beginrd_rdrdy<=1'b0;endelsebeginrd_rdrdy<=rd_en; endendregen; always@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)beginen<=1'b0;endelsebeginen<=rd_rdrdy; endendfifouut_fifo( .clk(clk), //inputclk .rst(~rst_n), //inputrst .din(wr_data), //input [7 : 0] din .wr_en(wr_en), //inputwr_en .rd_en(rd_en), //inputrd_en .dout(fifo_rddb), //output [7 : 0] dout .full(fifo_full), //outputfull .empty(fifo_empty) //outputempty); reg[3:0]ram_add; reg[7:0]ram_data; always@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)beginram_add<=1'b0;endelseif(rd_rdrdy==1'b1)beginram_add<=ram_add+1'b1;endelseif(cnt>9'd40&&cnt<9'd57)beginram_add<=ram_add+1'b1;endelsebeginram_add<=1'b0;endendalways@(posedgeclkornegedgerst_n)beginif(rst_n==1'b0)beginram_data=1'b0;endelseif(rd_rdrdy==1'b1)beginram_data=fifo_rddb; endelseif(cnt>9'd40&&cnt<9'd57)beginram_data=1'b0;endelsebeginram_data=1'b0;endendramuut_ram( .clka(clk), //inputclka .wea(en), //input [0 : 0] wea .addra(ram_add), //input [3 : 0] addra .dina(ram_data), //input [7 : 0] dina .douta(ram_rddb) //output [7 : 0] douta ); endmodule
