CNT138T

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT138T IS
PORT(CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(0 to 7));
END CNT138T;
ARCHITECTURE bhv OF CNT138T IS
SIGNAL Q1:STD_LOGIC_VECTOR(0 TO 7);
BEGIN
PROCESS(CLK) BEGIN
IF CLK’EVENT AND CLK=‘1’ THEN
IF Q1<“10001010” THEN Q1<=Q1+1;
ELSE Q1<=“00000000”;
END IF;
END IF;
END PROCESS;
Q<=Q1;
END bhv;