VHDL十大经典基础功能设计实例代码合集
一、文档概述
VHDL是硬件描述语言核心标准，广泛应用于FPGA、ASIC开发，入门阶段掌握基础逻辑、时序、计数器、状态机等经典模块是硬件开发必备能力。本文整理10个高频经典VHDL工程案例，覆盖组合逻辑、时序逻辑、分频、移位寄存器、状态机等核心场景，每个案例附带可直接综合、仿真的完整代码，适配Quartus、Vivado主流开发工具，适合硬件初学者快速上手实操。
二、十大经典VHDL案例代码演示
案例1：二输入与门（组合逻辑基础）
最简组合逻辑，理解实体、结构体基础语法
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a,b : in std_logic;
y : out std_logic
);
end entity and2;
architecture behav of and2 is
begin
y <= a and b;
end architecture behav;
案例2：4位二进制加法器
多位运算基础，掌握矢量信号使用
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add4 is
port(
num1,num2 : in std_logic_vector(3 downto 0);
sum_out : out std_logic_vector(3 downto 0);
carry : out std_logic
);
end add4;
architecture behav of add4 is
signal temp : std_logic_vector(4 downto 0);
begin
temp <= ('0' & num1) + num2;
sum_out <= temp(3 downto 0);
carry <= temp(4);
end behav;
案例3：D触发器（基础时序单元）
时序逻辑入门，时钟、复位信号标准写法
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(
clk,rst,d : in std_logic;
q : out std_logic
);
end dff;
architecture behav of dff is
begin
process(clk,rst)
begin
if rst = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
end behav;
案例4：8位同步计数器
掌握时序进程、循环计数逻辑
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt8 is
port(
clk,rst : in std_logic;
cnt_out : out std_logic_vector(7 downto 0)
);
end cnt8;
architecture behav of cnt8 is
signal cnt : std_logic_vector(7 downto 0);
begin
process(clk,rst)
begin
if rst='1' then
cnt <= (others=>'0');
elsif rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process;
cnt_out <= cnt;
end behav;
案例5：二分频电路
时钟分频最常用基础模块
library ieee;
use ieee.std_logic_1164.all;
entity div2 is
port(
clk_in,rst : in std_logic;
clk_out : out std_logic
);
end div2;
architecture behav of div2 is
signal temp : std_logic;
begin
process(clk_in,rst)
begin
if rst='1' then
temp <= '0';
elsif rising_edge(clk_in) then
temp <= not temp;
end if;
end process;
clk_out <= temp;
end behav;
案例6：4位移位寄存器
串行数据传输基础模块
library ieee;
use ieee.std_logic_1164.all;
entity shift4 is
port(
clk,rst,sin : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end shift4;
architecture behav of shift4 is
signal reg : std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst='1' then
reg <= "0000";
elsif rising_edge(clk) then
reg <= reg(2 downto 0) & sin;
end if;
end process;
q <= reg;
end behav;
案例7：3-8译码器
地址译码、外设选通核心电路
library ieee;
use ieee.std_logic_1164.all;
entity decoder38 is
port(
din : in std_logic_vector(2 downto 0);
dout: out std_logic_vector(7 downto 0)
);
end decoder38;
architecture behav of decoder38 is
begin
with din select
dout <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
end behav;
案例8：多路选择器MUX8to1
数据通路切换通用模块
library ieee;
use ieee.std_logic_1164.all;
entity mux8_1 is
port(
sel : in std_logic_vector(2 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic
);
end mux8_1;
architecture behav of mux8_1 is
begin
with sel select
dataout <= datain(0) when "000",
datain(1) when "001",
datain(2) when "010",
datain(3) when "011",
datain(4) when "100",
datain(5) when "101",
datain(6) when "110",
datain(7) when others;
end behav;
案例9：奇偶校验电路
通信数据校验基础设计
library ieee;
use ieee.std_logic_1164.all;
entity parity is
port(
din : in std_logic_vector(7 downto 0);
parity_bit : out std_logic
);
end parity;
architecture behav of parity is
begin
parity_bit <= din(0) xor din(1) xor din(2) xor din(3)
xor din(4) xor din(5) xor din(6) xor din(7);
end behav;
案例10：三段式有限状态机FSM
复杂时序逻辑标准开发范式
library ieee;
use ieee.std_logic_1164.all;
entity fsm3seg is
type state_type is (s0,s1,s2,s3);
port(
clk,rst,start : in std_logic;
state_out : out std_logic_vector(1 downto 0)
);
end fsm3seg;
architecture behav of fsm3seg is
signal curr_state,next_state : state_type;
begin
--第一段：时序逻辑 状态寄存
process(clk,rst)
begin
if rst='1' then
curr_state <= s0;
elsif rising_edge(clk) then
curr_state <= next_state;
end if;
end process;
--第二段：组合逻辑 状态跳转
process(curr_state,start)
begin
case curr_state is
when s0 => if start='1' then next_state<=s1; else next_state<=s0; end if;
when s1 => next_state <= s2;
when s2 => next_state <= s3;
when s3 => next_state <= s0;
end case;
end process;
--第三段：组合逻辑 输出逻辑
with curr_state select
state_out <= "00" when s0,
"01" when s1,
"10" when s2,
"11" when s3;
end behav;
三、使用说明
- 编译环境：代码兼容Vivado 2018+、Quartus II 13.0及以上版本；
- 仿真操作：新建工程，复制对应模块代码，添加testbench即可完成波形仿真；
- 综合注意：时序模块务必同步复位/异步复位规范书写，避免亚稳态；
- 拓展方向：可基于计数器、分频器组合设计计时器、流水灯等综合项目。
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