LabVIEW中心对齐的PWM输出
VI演示如何创建居中对齐的PWM输出。
描述
该代码块产生一个中心对齐的PWM输出,用于运动控制应用。在FET或IGBT桥(如H桥)中,使用中心对齐的PWM意味着开关改变状态的频率是使用普通PWM信号时的一半。这减少了开关上的磨损,减少了FET或IGBT产生的热量,并改善了系统的动态特性。该代码设计为在单周期定时环路中运行,因此,通过cRIO或FPGA卡上的高速数字输出,PWM信号可以在FPGA时钟周期上更新。它也可以在窗口和实时目标上执行。
下图在上图中显示了两个正常的PWM信号,第一个占空比为20%,第二个占空比为10%。第二张图显示了使用中心对齐的PWM输出的相同PWM信号。
要求
软件
LabVIEW完整或专业开发系统2012(或兼容)
如果在实时环境中运行,需要LabVIEW实时模块2012(或兼容)
如果在FPGA环境中运行,需要LabVIEWFPGA模块2012(或兼容)
硬件
FPGA和实时目标可选(例如cRIO9074或兼容)
Overview
Thisexample demonstrates how to create a center-aligned PWM output.
Description
Thisblock of code produces a center-aligned PWM output to be used in motion controlapplications. In a FET or IGBT bridge such as an H-bridge, use of acenter-aligned PWM means that the switches change state half as frequently asthey would when using a normal PWM signal. This reduces wear on the switches,decreases the heat generated by the FETs or IGBTs and also improves the dynamiccharacteristics of the system. The code has been designed to run in asingle-cycle timed loop so that with a high-speed digital output on a cRIO orFPGA card, the PWM signal can update on the FPGA clock cycle. It can also beexecuted on windows and real-time targets.
The imagebelow shows two normal PWM signals on the top graph, the first with a 20% dutycycle and the second with a 10% duty cycle. The second graph shows the same PWMsignals using the center-aligned PWM output.
Requirements
Software
LabVIEWFull or Professional Development System 2012 (or compatible)
Ifrunning in a Real-Time context, you will need the LabVIEW Real-Time Module 2012(or compatible)
Ifrunning in a FPGA context, you will need the LabVIEW FPGA Module 2012 (orcompatible)
Hardware
FPGA andReal-Time target optional (e.g. cRIO 9074 or compatible)
Steps to Implement or Execute Code
Downloadand open the attached file "Center-Aligned PWM Generation LV2012NIVerified.vi"
Followthe instructions in Front Panel and Block Diagram and run the program
Additional Information or References
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LabVIEW程序,如下附件所示。