数字逻辑电路设计实验：七段数码管译码器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dtsm is
  port(clk:in std_logic;
  key:in std_logic_vector(3 downto 0);
  ledag:out std_logic_vector(6 downto 0);
  sel:out std_logic_vector(2 downto 0)
);
end dtsm;
architecture beha of dtsm is
  begin 
  process(clk)
  variable count:std_logic_vector(2 downto 0);
    begin
    if(clk'event and clk='1') then
      count:=count+'1';
    --if(count="111") then count:="000"; end if;
    end if;
    sel<=count;
  end process;
  process(key)
    begin
    if (sel>"010") then
    case key is
      when "0000"=> ledag<="0111111";
      when "0001"=> ledag<="0000110";
      when "0010"=> ledag<="1011011";
      when "0011"=> ledag<="1001111";
      when "0100"=> ledag<="1100110";
      when "0101"=> ledag<="1101101";
      when "0110"=> ledag<="1111101";
      when "0111"=> ledag<="0000111";
      when "1000"=> ledag<="1111111";
      when "1001"=> ledag<="1101111";
      when "1010"=> ledag<="1110111";
      when "1011"=> ledag<="1111100";
      when "1100"=> ledag<="0111001";
      when "1101"=> ledag<="1011110";
      when "1110"=> ledag<="1111001";
      when "1111"=> ledag<="1110001";
    end case;
  else
    case key is
      when "0001"=> ledag<="0111111";
      when "0010"=> ledag<="0000110";
      when "0011"=> ledag<="1011011";
      when "0100"=> ledag<="1001111";
      when "0101"=> ledag<="1100110";
      when "0110"=> ledag<="1101101";
      when "0111"=> ledag<="1111101";
      when "1000"=> ledag<="0000111";
      when "1001"=> ledag<="1111111";
      when "1010"=> ledag<="1101111";
      when "1011"=> ledag<="1110111";
      when "1100"=> ledag<="1111100";
      when "1101"=> ledag<="0111001";
      when "1110"=> ledag<="1011110";
      when "1111"=> ledag<="1111001";
      when "0000"=> ledag<="1110001";
    end case;
  end if;
end process;
end beha;