VL34 整数倍数据位宽转换8to16
`timescale 1ns/1ns module width_8to16( input clk , input rst_n , input valid_in , input [ 7:0] data_in , output reg valid_out , output reg [ 15:0] data_out ); reg data_cnt ; //计数器用于表示计算是否满 always @(posedge clk or negedge rst_n) begin if(!rst_n) begin data_cnt <= 1'b0; end else begin if(valid_in) begin data_cnt <= data_cnt + 1'b1; end else begin data_cnt <= data_cnt; end end end reg [7:0] data_reg; always @(posedge clk or negedge rst_n) begin if(!rst_n) begin data_out <= 16'b0; valid_out <= 1'b0; end else begin if (valid_in) begin if (data_cnt == 0) begin data_reg <= data_in; valid_out <= 1'b0; end else begin data_out <= {data_reg,data_in}; valid_out <= 1'b1; end end else begin valid_out <= 1'b0; end end end endmodule
VL35 状态机-非重叠的序列检测
`timescale 1ns/1ns module sequence_test1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// parameter IDLE = 3'b000; parameter s1_1 = 3'b001; parameter s2_10 = 3'b010; parameter s3_101 = 3'b011; parameter s4_1011 = 3'b100; parameter s5_10111 = 3'b101; //machine variable reg [ 2:0] st_next ; reg [ 2:0] st_cur ; //(1) state transfer always @(posedge clk or negedge rst) begin if (!rst) begin st_cur <= IDLE ; end else begin st_cur <= st_next ; end end always @(*) begin case (st_cur) IDLE: begin st_next = data?s1_1:IDLE; end s1_1: begin st_next = data?s1_1:s2_10; end s2_10: begin st_next = data?s3_101:IDLE; end s3_101: begin st_next = data?s4_1011:s2_10; end s4_1011: begin st_next = data?s5_10111:s2_10; end s5_10111:begin st_next = data?s1_1:IDLE; end default: st_next = IDLE; endcase end always @(*) begin if(!rst) begin flag <= 1'b0; end else if(st_cur == s5_10111) begin flag <= 1'b1; end else begin flag <= 1'b0; end end //*************code***********// endmodule
VL36 状态机-重叠序列检测
`timescale 1ns/1ns module sequence_test2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// parameter S0=0, S1=1, S2=2, S3=3, S4=4; reg [2:0] state, nstate; always@(posedge clk or negedge rst) begin if(~rst) state <= S0; else state <= nstate; end always@(*) begin if(~rst) nstate <= S0; else case(state) S0 : nstate <= data? S1: S0; S1 : nstate <= data? S1: S2; S2 : nstate <= data? S3: S0; S3 : nstate <= data? S4: S2; S4 : nstate <= data? S1: S2; default: nstate <= S0; endcase end always@(posedge clk or negedge rst) begin if(~rst) flag <= 0; else flag <= state==S4; end //*************code***********// endmodule
VL37 时钟分频（偶数）
`timescale 1ns/1ns module even_div ( input wire rst , input wire clk_in , output wire clk_out2 , output wire clk_out4 , output wire clk_out8 ); //*************code***********// reg [ 1:0] clk_cnt ; reg s_1,s_2,s_3 ; always @(posedge clk_in or negedge rst) begin if(!rst) begin clk_cnt <= 2'b0; end else if (clk_cnt == 2'b11) begin clk_cnt <= 2'b0; end else begin clk_cnt <= clk_cnt + 1'b1; end end always @(posedge clk_in or negedge rst) begin if (!rst) begin s_1 <= 1'b0; s_2 <= 1'b0; s_3 <= 1'b0; end else begin if(clk_cnt==2'd0 ||clk_cnt==2'd1||clk_cnt==2'd2||clk_cnt==2'd3) begin s_1 <= ~s_1; end if (clk_cnt == 2'd0 || clk_cnt == 2'd2) begin s_2 <= ~s_2; end if(clk_cnt == 2'd0) begin s_3 <= ~s_3; end end end assign clk_out2 = s_1; assign clk_out4 = s_2; assign clk_out8 = s_3; //*************code***********// endmodule
VL38 自动贩售机1
`timescale 1ns/1ns module seller1( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire d3 , output reg out1, output reg [1:0]out2 ); //*************code***********// localparam IDLE = 0, HALF = 1, ONE = 2, ONE_HALF = 3, TWO = 4, TWO_HALF = 5, THREE =6; reg[2:0] curr_state,next_state; always @(posedge clk or negedge rst)begin if(~rst) curr_state <= IDLE; else curr_state <= next_state; end always @(*)begin case(curr_state) IDLE :begin next_state =d1? HALF: d2? ONE: d3? TWO: next_state; end HALF :begin next_state =d1? ONE: d2? ONE_HALF: d3? TWO_HALF: next_state; end ONE :begin next_state =d1? ONE_HALF: d2? TWO: d3? THREE: next_state; end ONE_HALF :next_state =IDLE; TWO :next_state =IDLE; TWO_HALF :next_state =IDLE; THREE :next_state =IDLE; default :next_state =IDLE; endcase end always @(posedge clk or negedge rst)begin if(~rst)begin out1 <= 0; out2 <= 0; end else begin case(next_state) ONE_HALF:begin out1 <= 1'b1; out2<=0; end TWO :begin out1 <= 1'b1; out2<=1; end TWO_HALF:begin out1 <= 1'b1; out2<=2; end THREE :begin out1 <= 1'b1; out2<=3; end default :begin out1 <= 1'b0; out2<=0; end endcase end end //*************code***********// endmodule
VL39 自动贩售机2
`timescale 1ns/1ns module seller2( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire sel , output reg out1, output reg out2, output reg out3 ); //*************code***********// //*************code***********// endmodule
VL40 占空比50%的奇数分频
`timescale 1ns/1ns module odo_div_or ( input wire rst , input wire clk_in , output wire clk_out7 ); //*************code***********// //*************code***********// reg [ 2:0] clk_cnt ; always @(posedge clk_in or negedge rst) begin if(!rst) begin clk_cnt <= 3'b0; end else if (clk_cnt == 3'd6) begin clk_cnt <= 3'b0; end else begin clk_cnt <= clk_cnt + 1'b1; end end reg s_1 ; always @(posedge clk_in or negedge rst) begin if (!rst) begin s_1 <= 1'b0; end else begin if(clk_cnt == 3'd6) begin s_1 <= ~s_1; end else begin s_1 <= s_1; end end end always @(negedge clk_in or negedge rst) begin if (!rst) begin s_1 <= 1'b0; end else begin if(clk_cnt == 3'd3) begin s_1 <= ~s_1; end else begin s_1 <= s_1; end end end assign clk_out7 = s_1; //*************code***********// endmodule
VL41 任意小数分频
`timescale 1ns/1ns module div_M_N( input wire clk_in , input wire rst , output wire clk_out ); parameter M_N = 8'd87 ; parameter c89 = 8'd24 ;//8/9时钟切换点 parameter div_e = 5'd8 ;//偶数周期 parameter div_o = 5'd9 ;//奇数周期 //*************code***********// reg [ 6:0] data_cnt ; always @(posedge clk_in or negedge rst) begin if (!rst) begin data_cnt <= 7'd0; end else begin if(data_cnt == 7'd86) begin data_cnt <= 0; end else begin data_cnt <= data_cnt + 1'd1; end end end reg clk_out_ache ; always @(posedge clk_in or negedge rst) begin if (!rst) begin clk_out_ache <= 1'd0; end else begin if(data_cnt < c89) begin // if (data_cnt < 3) begin // clk_out_ache <= 1'b1; // end if(data_cnt == 0|| data_cnt == 4|| data_cnt == 8|| data_cnt == 12|| data_cnt == 16|| data_cnt == 20) begin clk_out_ache <= ~clk_out_ache; end else begin clk_out_ache <= clk_out_ache; end end else if(data_cnt == 24 ||data_cnt==28 || data_cnt == 33 ||data_cnt==37 || data_cnt == 42 ||data_cnt==46 || data_cnt == 51 ||data_cnt==55 || data_cnt == 60 ||data_cnt==64 || data_cnt == 69 ||data_cnt==73 || data_cnt == 78 ||data_cnt==82 )begin clk_out_ache <= ~clk_out_ache; end else begin clk_out_ache <= clk_out_ache; end end end assign clk_out = clk_out_ache; endmodule
