`default_nettype none 
module VirtualBoard (
    input  logic  CLOCK,      // 10 MHz Input Clock 
    input  logic [19:0] PB,   // 20 Push Buttons, logical 1 when pressed
    input  logic [35:0] S,    // 36 Switches
    output logic [35:0] L,    // 36 LEDs, drive logical 1 to light up
    output logic  [7:0] SD7,  // 8 common anode Seven-segment Display
    output logic  [7:0] SD6,
    output logic  [7:0] SD5,
    output logic  [7:0] SD4,
    output logic  [7:0] SD3,
    output logic  [7:0] SD2,
    output logic  [7:0] SD1,
    output logic  [7:0] SD0
);
/********* Seven-segment decoder instantiation **********/
logic [3:0] HD[7:0];  // 8 hexadecimal display 
SevenSegDecode ssdecode_inst7(.iData(HD[7]), .oSeg(SD7));
SevenSegDecode ssdecode_inst6(.iData(HD[6]), .oSeg(SD6));
SevenSegDecode ssdecode_inst5(.iData(HD[5]), .oSeg(SD5));
SevenSegDecode ssdecode_inst4(.iData(HD[4]), .oSeg(SD4));
SevenSegDecode ssdecode_inst3(.iData(HD[3]), .oSeg(SD3));
SevenSegDecode ssdecode_inst2(.iData(HD[2]), .oSeg(SD2));
SevenSegDecode ssdecode_inst1(.iData(HD[1]), .oSeg(SD1));
SevenSegDecode ssdecode_inst0(.iData(HD[0]), .oSeg(SD0));
/** The input port is replaced with an internal signal **/
wire reset  = PB[0];
wire clk    = PB[1];
wire [3:0] DATA  = S[3:0];
wire [1:0] INDEX = S[5:4];
wire RFoe   = S[6];
wire GRSoe = S[7];
wire DATAoe= S[8];
wire [3:0] ALUop = S[12:9];
// wire    = S[13];
wire RFce = S[14];
wire PSWce= S[15];
wire GRSce= S[16];
wire RXce = S[17];
/************* The logic of this experiment *************/
//各模块间连线信号
wire [3:0] BUS, RX_Q, F, RF_Q, GRS_Q;
wire [3:0] FLAG, PSW_Q;
//模块实例
ALU #(4) ALU_inst(.iOp(ALUop), .iX(RX_Q), .iY(BUS), .oF(F), .oFlag(FLAG), .Cin(PSW_Q[0]));
GRS #(4) GRS_inst(.iD(BUS), .oQ (GRS_Q), .Load(GRSce), .Clk(clk), .Index(INDEX));
DataReg #(4) RX_inst(.oQ(RX_Q), .iD(BUS), .Clk(clk), .Load(RXce), .Reset(reset));
DataReg #(4) RF_inst(.oQ(RF_Q), .iD(F), .Clk(clk), .Load(RFce), .Reset(reset));
DataReg #(4) PSW_inst(.oQ(PSW_Q), .iD(FLAG), .Clk(clk), .Load(PSWce ), .Reset(reset));
//三态缓冲器逻辑描述
assign BUS = RFoe   ? RF_Q  : 4'bzzzz;
assign BUS = GRSoe  ? GRS_Q : 4'bzzzz;
assign BUS = DATAoe ? DATA  : 4'bzzzz;
/****** Internal signal assignment to output port *******/
assign L[25:22] = PSW_Q;
assign L[21:18] = FLAG;
assign HD[5] = RX_Q;
assign HD[4] = BUS;
assign HD[3] = GRS_Q;
assign HD[1] = RF_Q;
assign HD[0] = F;
endmodule

`default_nettype none 
module VirtualBoard (
    input  logic  CLOCK,      // 10 MHz Input Clock 
    input  logic [19:0] PB,   // 20 Push Buttons, logical 1 when pressed
    input  logic [35:0] S,    // 36 Switches
    output logic [35:0] L,    // 36 LEDs, drive logical 1 to light up
    output logic  [7:0] SD7,  // 8 common anode Seven-segment Display
    output logic  [7:0] SD6,
    output logic  [7:0] SD5,
    output logic  [7:0] SD4,
    output logic  [7:0] SD3,
    output logic  [7:0] SD2,
    output logic  [7:0] SD1,
    output logic  [7:0] SD0
);
/********* Seven-segment decoder instantiation **********/
logic [3:0] HD[7:0];  // 8 hexadecimal display 
SevenSegDecode ssdecode_inst7(.iData(HD[7]), .oSeg(SD7));
SevenSegDecode ssdecode_inst6(.iData(HD[6]), .oSeg(SD6));
SevenSegDecode ssdecode_inst5(.iData(HD[5]), .oSeg(SD5));
SevenSegDecode ssdecode_inst4(.iData(HD[4]), .oSeg(SD4));
SevenSegDecode ssdecode_inst3(.iData(HD[3]), .oSeg(SD3));
SevenSegDecode ssdecode_inst2(.iData(HD[2]), .oSeg(SD2));
SevenSegDecode ssdecode_inst1(.iData(HD[1]), .oSeg(SD1));
SevenSegDecode ssdecode_inst0(.iData(HD[0]), .oSeg(SD0));
/** The input port is replaced with an internal signal **/
wire reset  = PB[0];
wire clk    = PB[1];
wire [1:0] RA2  = S[3:2];
wire [1:0] RA1  = S[1:0];
wire [1:0] WA=S[5:4];
wire WE   = S[6];
wire [3:0] ALUop = S[11:8];
wire M0 = S[14];
wire S1 = S[13];
wire S0 = S[12];
wire RXce = S[17];
/************* The logic of this experiment *************/
//各模块间连线信号
wire [3:0] RD1;
wire [3:0] RD2;
wire [3:0] FLAG;
wire [3:0] SSD3;
wire [3:0] SSD0;
//模块实例
sALU #(4) ALU_inst(.iCtrl(ctrl), .iX(RD1), .iY(SSD0), .oF(SSD3), .oFlag(FLAG));
RegFile #(4) GRS_inst(.iRA1(RA1),.iRA2(RA2),.iWA(WA),.iWE(WE),.Clk(clk),.iWD(SSD3),.oRD1(RD1),.oRD2(RD2));
//三态缓冲器逻辑描述
wire [2:0] ctrl=S[14:12];
always_comb
begin
  case (S[7])
    1'b1: SSD0=ALUop;
    1'b0: SSD0=RD2;
    default: SSD0={4{1'bx}};
  endcase
end
/****** Internal signal assignment to output port *******/
assign HD[3] = SSD3;
assign HD[2] = RD2;
assign HD[1] = RD1;
assign HD[0] = SSD0;
assign L[21:18]=FLAG;
endmodule