数控分频模块

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY spker IS
  PORT(clk:IN STD_LOGIC;
       Tn:IN STD_LOGIC_VECTOR(0 TO 10);
       SpkS:OUT STD_LOGIC);
END spker;
ARCHITECTURE behav OF spker IS
  SIGNAL Q:STD_LOGIC_VECTOR(0 TO 10);
BEGIN
  PROCESS(CLK)  BEGIN
    IF CLK'EVENT AND CLK='1' THEN
      IF Q<"11111111111" THEN Q<=Q+1;SpkS <='0';
      elsif Q="11111111111" THEN Q<=Tn; SpkS <='1';
      END IF;
    END IF;
  END PROCESS; 
END behav;